Integrated
Circuit
Systems, Inc.
ICS9219
Direct Rambus™ Clock Generator Lite
General Description
ICS9219
is a High-speed clock generator providing 400 or
533 MHz differential clock source for direct Rambus
memory system.
ICS9219
takes a crystal as an input
reference source, and produces the differential output
clock required for the Rambus channel.
ICS9219
provides
a solution for a broad range of Direct Rambus memory
applications.
ICS9219
can be used in single or dual
Rambus channels. An additional LVCMOS output, which
provides a reference clock at the crystal frequency for the
other system blocks is also included.
Features
•
•
•
•
•
•
Compatible with all Direct Rambus
TM
based ICs
Provides differential clock source for direct
Rambus memory system with 1GHz data transfer
rate capability
Cycle to Cycle jitter is less than 100ps
3.3V + 4% supply
LVCMOS REF clock @ crystal frequency
Output edge rate control to minimize EMI
Block Diagram
FS0
X1
X2
Pin Configuration
VDDT
GND
X2
X1
VDD
REF
GND
FS1*
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
FS0*
VDD
GND
BUSCLKT
BUSCLKC
GND
VDD
FS2*
PLL
REF
VDDT
FS1
FS2
Control
Logic
16-Pin 173 mil TSSOP
* Pins have 60K internal pull-up to VDD
Table 1. PLL Multiplier Selection and Output Frequency
FS0
0
1
Mult
16
21.33
2
BUSCLK
1
400.00
533.30
Notes:
1 Output frequencies are based on 25MHz XTAL Input
multipliers are also applicable to spread spectrum modulated input clocks.
2 Default muliplier value at power up.
0931B—10/25/04
ICS9219
Xtal
OSC
BUSCLKT
BUSCLKC
ICS9219
Pin Descriptions
PIN #
1
2
3
4
5
6
7
8
9
10
11
12
13
PIN NAME
VDDT
GND
X2
X1
VDD
REF
GND
FS1*
FS2*
VDD
GND
BUSCLKC
BUSCLKT
PIN TYPE
PWR/IN
PWR
OUT
IN
PWR
OUT
PWR
IN
IN
PWR
PWR
OUT
OUT
DESCRIPTION
Power supply, nominal 3.3V/Test mode
Ground pin.
Crystal output (14MHz to 25MHz)
Crystal input (14MHz to 25MHz)
Power supply, nominal 3.3V
Reference of Input
Ground pin.
Frequency select pin.
Real-time frequency select pin with internal 120Kohm pull-up resistor (check
SMBus HW/SW setting for priority).
Power supply, nominal 3.3V
Ground pin.
Output clock connected to the Rambus channel. This output is the complement
of BUSCLK.
Output clock connected to the Rambus channel. This output is the true
component of BUSCLK.
Ground pin.
Power supply, nominal 3.3V
Frequency select pin.
14
GND
PWR
15
VDD
PWR
16
FS0*
IN
* Pins have 60K internal pull-up to VDD
Table 2: Function Table
FS(2:0)
INPUT
VDDT
MULT
FS2
FS1
FS0
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
0
0
0
0
0
1
1
0
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
X
X
X
X
X
X
16
21.33
16
21.33
-
-
-
-
-
-
MODE
NORMAL
NORMAL
NORMAL
NORMAL
TEST
TEST
TEST
TEST
TEST
TEST
BUSCLKT
INPUT x MULT
INPUT x MULT
INPUT x MULT
INPUT x MULT
BUSCLKT/2
BUSCLKT/4
X1
X1
X1/2
X1/4
BUSCLKC
BUSCLKC
BUSCLKC
BUSCLKC
BUSCLKC
BUSCLKC/2
BUSCLKC/4
X1(INVERT)
X1(INVERT)
X1(INVERT)/2
X1(INVERT)/4
REF
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
0931B—10/25/04
2
ICS9219
Absolute Maximum Ratings over operating free-air temperature
Supply voltage range, V
DD
or V
DDT
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 4 V
Input voltage range,V
I
, at any input terminal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to V
DD
+ 0.5 V
Output voltage range, V
O
, at any output terminal (BUSCLKT/C) . . . . . . . . . . . . . . . . . . . . -0.5 V to V
DD
+ 0.5 V
ESD rating (MIL-STD 883C, Method 3015) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . > 2 kV, Machine Model >200 V
Operating free-air temperature range, T
A
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
0
˚C to 85˚C
Storage temperature range, T
stg
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65˚C
to 150˚C
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to the GND terminals.
Recommended Operating Conditions
Supply voltage, V
DD
Low-level input voltage, V
IL
High-level input voltage, V
IH
Internal pullup resistance
Input frequency at crystal input
Low-level output current, I
OL
High-level output current, I
OH
Input capacitance (CMOS), C
L
Operating free-air temperature
FS (2:0)
X1, X2
0
MIN
3
FS (2:0)
FS (2:0)
FS (2:0)
0.65 x V
DD
90
14.0625
BUSCLKT/C
REF
BUSCLKT/C
REF
NOM
3.3
MAX
3.6
0.35 x V
DD
150
26
16
10
-16
-10
15
15
85
UNIT
V
V
kΩ
MHz
mA
mA
pF
C
25
Timing Requirements
Clock cycle time, t
(CYCLE)
Input slew rate, S
R
State transition latency (V
DDX
or S0 to CLKs - normal mode), t
(STL)
MIN
2.5
0.5
MAX
3.7
4
3
UNIT
ns
V/ns
ms
Crystal Specifications
Frequency
Frequency tolerance (at 25°C) ± 3°C)
Equivalent resistance (C
L
= 10 pF)
Temperature drift (-10°C to 75°C)
Drive level
Motional inductance
Insulation resistance
Spurious attenuation ratio (at frequency ±500 kHz)
Overtone spurious
0931B—10/25/04
MIN
14.0625
-15
0.01
20.7
500
3
8
MAX
26
15
100
10
1500
25.3
UNIT
MHz
ppm
Ω
ppm
µΩ
mH
MΩ
dB
dB
3
ICS9219
Electrical Characteristics over Recommended Operating Free-Air Temperature
PARAMETER
V
X
V
COS
V
IK
R
I
I
IH
Differential crossing-point output
voltage
Peak-to-peak output voltage swing,
single ended
Input clamp voltage
Input resistance
High-level input
current
X1, X2
X2
FS0
FS1, FS2
I
IL
Low-level input
current
X2
FS0
FS1, FS2
High-level output
voltage
BUSCLKT/C,
REF
TEST CO NDITIO NS*
See Figures 1 and 2
V
OH
- V
OL
V
DD
= 3V
V
DD
= 3.3V
V
DD
= 3.3V
V
DD
= 3.6V
V
DD
= 3.6V
V
DD
= 3.6V
V
DD
= 3.6V
V
DD
= 3.6V
See Figure 1
V
OH
V
DD
= min to max
V
DD
= 3V
V
OL
Low-level output
voltage
High-level output
current
Low-level output
current
BUSCLKT/C,
REF
BUSCLKT/C,
REF
BUSCLKT/C,
REF
4
MIN
1.25
0.4
TYP**
1.6
0.6
MAX
1.85
0.7
-1.2
UNIT
V
V
V
k
mA
mA
mA
mA
See Figure 1
I
I
= -18 mA
V
I
= V
O
V
O
= 2V
V
I
= V
DD
V
I
= V
DD
V
O
= 0V
V
I
= 0V
V
I
= 0V
>50
27
10
10
-5.7
-30
-10
V
DD
-
0.1V
2.2
1
2.5
0.05
0.25
-50
-50
-21
43
-15
69
69
30
12
12
25
17
36
40
40
3
0.1
0.5
-32
-100
-50
2.1
I
OH
= -1 mA
I
OH
= -16 mA
I
OH
= 1 mA
I
OH
= 16 mA
V
O
= 1V
V
O
= 1.65V
V
O
= 3.135V
V
O
= 1.95V
V
O
= 1.65V
V
O
= 0.9V
V
See Figure 1
V
DD
= min to max
V
DD
= 3V
V
DD
= 3.135V
V
DD
= 3.3V
V
DD
= 3.465V
V
DD
= 3.135V
V
DD
= 3.3V
V
DD
= 3.465V
V
I
OH
mA
I
OL
r
OH
r
OL
C
O
I
DD
I
DDL
I
DD (NORMA L)
mA
High-level dynamic output resistance
∠
I
O
- 14.5 mA to
∠
I
O
- 16.5 mA
∠
I
O
- 14.5 mA to
∠
I
O
- 16.5 mA
Low-level dynamic output resistance
4
O utput capacitance
BUSCLKT,
BUSCLKC, REF
Static supply current
pF
mA
mA
mA
mA
O utputs high or low (V
DDT
= 0V)
O utputs high or low (V
DDT
= 0V)
400 MHz
533MHz
84
91
6.5
50
100
120
Static supply current
Supply current in normal state
* V
DD
refers to any of the following: V
DD,
V
DDT
.
** All typical values are at V
DD
= 3.3V, T
A
25°C.
4
r
O
=
∠
V
O
/
∠
I
O
. This is defined at the output terminals, not at the measurement point of figure 1.
0931B—10/25/04
4
ICS9219
Switching Characteristics over Recommended Operating Free-Air Temperature Range.
PARAMETER
t
(CYCLE)
t
J
t
JL
D
C
t
DC,ERR
t
CR
, t
DF
∆t
RF
t
CYCLE(L)
t
(CJ)
t
(CJ10)
D
C(2)
t
CRL
, t
CFL
Clock cycle time (BUSCLKT/C)
Total jitter over 1, 2, 3, 4, 5 or 6 clock
cycles
Long-term jitter
400 MHz
533 MHz
400 MHz
533 MHz
400 MHz
533 MHz
See Figure 3
See Figure 4
See Figure 5
See Figure 6
See Figure 7
See Figure 7
80
See Figure 8
Measured at 50%
REF
REF
See Figure 7
fmod = 50 kHz
fmod = 8 MHz
-20
-0.2
-1.3 t
(CJ)
47%
50
0.8
0.1
43%
51
30
30
120
250
50
TEST CONDITIONS*
MIN
1.8
42
33
TYP**
MAX
3.7
50
50
300
300
53%
50
50
400
100
142.2
0.2
1.3 t
(CJ)
53%
1
-3
ns
dB
ps
UNIT
ns
ps
ps
Output duty cycle over 10,000 cycles
Output cycle-to-cycle duty cycle error
Output rise and fall times (measured at
BUSCLKT/C
20%-80% of output voltage)
Difference between rise and fall times on a single
device (20% ± 80%) |tCR - tCF|
Clock cycle time (REF)
REF cycle jitter
REF 10-cycle jitter
Output duty cycle
Output rise and fall times (measured at
20%-80% of output voltage)
PLL loop bandwidth
ps
ps
ns
ns
ns
0931B—10/25/04
5
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