GS8322Z36GE-250T datasheet, PDF

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GS8322Z36GE-250T: DescriptionZBT SRAM, 1MX36, 6.5ns, CMOS, PBGA165, 15 X 17 MM, 1 MM PITCH, ROHS COMPLIANT, FPBGA-165; Categorystorage storage; File Size2MB，40 Pages; ManufacturerGSI Technology; Websitehttp://www.gsitechnology.com/; Environmental Compliance

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GS8322Z36GE-250T Overview

ZBT SRAM, 1MX36, 6.5ns, CMOS, PBGA165, 15 X 17 MM, 1 MM PITCH, ROHS COMPLIANT, FPBGA-165

GS8322Z36GE-250T Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	GSI Technology
Parts packaging code	BGA
package instruction	15 X 17 MM, 1 MM PITCH, ROHS COMPLIANT, FPBGA-165
Contacts	165
Reach Compliance Code	compliant
ECCN code	3A991.B.2.B
Maximum access time	6.5 ns
Other features	FLOW-THROUGH OR PIPELINED ARCHITECTURE; ALSO OPERATES AT 3.3V SUPPLY
JESD-30 code	R-PBGA-B165
JESD-609 code	e1
length	17 mm
memory density	37748736 bit
Memory IC Type	ZBT SRAM
memory width	36
Humidity sensitivity level	3
Number of functions	1
Number of terminals	165
word count	1048576 words
character code	1000000
Operating mode	SYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	1MX36
Package body material	PLASTIC/EPOXY
encapsulated code	LBGA
Package shape	RECTANGULAR
Package form	GRID ARRAY, LOW PROFILE
Parallel/Serial	PARALLEL
Peak Reflow Temperature (Celsius)	260
Certification status	Not Qualified
Maximum seat height	1.4 mm
Maximum supply voltage (Vsup)	2.7 V
Minimum supply voltage (Vsup)	2.3 V
Nominal supply voltage (Vsup)	2.5 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	Tin/Silver/Copper (Sn/Ag/Cu)
Terminal form	BALL
Terminal pitch	1 mm
Terminal location	BOTTOM
Maximum time at peak reflow temperature	NOT SPECIFIED
width	15 mm

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GS8322Z18(B/E)/GS8322Z36(B/E)/GS8322Z72(C)

119, 165 & 209 BGA

Commercial Temp

Industrial Temp

Features

• NBT (No Bus Turn Around) functionality allows zero wait

Read-Write-Read bus utilization; fully pin-compatible with

both pipelined and flow through NtRAM™, NoBL™ and

ZBT™ SRAMs

• 2.5 V or 3.3 V +10%/–10% core power supply

• 2.5 V or 3.3 V I/O supply

• User-configurable Pipeline and Flow Through mode

• ZQ mode pin for user-selectable high/low output drive

• IEEE 1149.1 JTAG-compatible Boundary Scan

• LBO pin for Linear or Interleave Burst mode

• Pin-compatible with 2Mb, 4Mb, 8Mb, and 16Mb devices

• Byte write operation (9-bit Bytes)

• 3 chip enable signals for easy depth expansion

• ZZ Pin for automatic power-down

• JEDEC-standard 119-, 165- or 209-Bump BGA package

• Pb-Free packages available

36Mb Pipelined and Flow Through

Synchronous NBT SRAM

250 MHz–133 MHz

2.5 V or 3.3 V V

2.5 V or 3.3 V I/O

Because it is a synchronous device, address, data inputs, and

read/write control inputs are captured on the rising edge of the

input clock. Burst order control (LBO) must be tied to a power

rail for proper operation. Asynchronous inputs include the

Sleep mode enable (ZZ) and Output Enable. Output Enable can

be used to override the synchronous control of the output

drivers and turn the RAM's output drivers off at any time.

Write cycles are internally self-timed and initiated by the rising

edge of the clock input. This feature eliminates complex off-

chip write pulse generation required by asynchronous SRAMs

and simplifies input signal timing.

The GS8322Z18/36/72 may be configured by the user to

operate in Pipeline or Flow Through mode. Operating as a

pipelined synchronous device, in addition to the rising-edge-

triggered registers that capture input signals, the device

incorporates a rising edge triggered output register. For read

cycles, pipelined SRAM output data is temporarily stored by

the edge-triggered output register during the access cycle and

then released to the output drivers at the next rising edge of

clock.

The GS8322Z18/36/72 is implemented with GSI's high

performance CMOS technology and is available in a JEDEC-

standard 119-bump, 165-bump or 209-bump BGA package.

Functional Description

The GS8322Z18/36/72 is a 36Mbit Synchronous Static

SRAM. GSI's NBT SRAMs, like ZBT, NtRAM, NoBL or

other pipelined read/double late write or flow through read/

single late write SRAMs, allow utilization of all available bus

bandwidth by eliminating the need to insert deselect cycles

when the device is switched from read to write cycles.

Parameter Synopsis

KQ(x18/x36)

KQ(x72)

tCycle

Curr

(x18)

Curr

(x36)

Curr

(x72)

tCycle

Curr

(x18)

Curr

(x36)

Curr

(x72)

-250 -225 -200

2.5 2.7 3.0

3.0 3.0 3.0

4.0 4.4 5.0

285

350

440

6.5

205

235

315

265

320

410

7.0

195

225

295

245

295

370

7.5

185

210

265

-166

3.5

6.0

220

260

320

8.0

175

200

255

-150

3.8

6.7

210

240

300

8.5

165

190

240

-133 Unit

4.0 ns

7.5 ns

185

215

265

8.5

155

175

230

Pipeline

3-1-1-1

Flow

Through

2-1-1-1

Rev: 1.07a 3/2009

1/40

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

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