Pm37LV512
512 Kbit (64K X 8) Dual-Voltage Multiple-Cycle-Programmable ROM
FEATURES
Low Voltage Operation
- Dual read V
CC
ranges: 2.7 V to 3.6 V or 4.5 V to
5.5 V
- Program/Erase voltage: V
CC
- 2.7 V to 3.6 V and
V
PP
- 11.5 V to 12.5 V
• High Performance Read
- 70 ns access time
• Electrical Chip Erase and Byte Program
Using EPROM Programmer
-
Maximum 20 µs/byte programming
- Maximum 100 ms chip erase
- Do not require UV erase
• Low Power Consumption
- Typical 5 mA active read current
- Typical 18 µA CMOS standby current
• Excellent Product Reliablity
- Guarantee minimum 1,000 program/erase cycles
- Minimum 20 years data retention
• JEDEC Standard Byte-wide Flash Memory
Pin-out
• Industrial Standard Packaging
- 32-pin PLCC
- 32-pin PDIP
- 32-pin VSOP
GENERAL DESCRIPTION
The Pm37LV512 is a 512 Kbit, Multiple-Cycle-Programmable Read-Only-Memory (MCP ROM) organized as 65,563
bytes of 8 bits each. The program and erase operation of device can be done on EPROM programmers by applying
3.0 Volt V
CC
and 12.0 Volt V
PP
to A9 and/or OE# pin. This eliminates the need of a UV-Source for erase operation
such as EPROM device. The read operation of device can be in 2.7 Volt to 3.6 Volt or 4.5 Volt - 5.5 Volt range
compatible to either 3.0 Volt or 5.0 Volt systems. The dual read operation ranges can greatly increase application
flexibility for users.
The device has a standard microprocessor interface as well as JEDEC single-power-supply Flash compatible pin-
out. For applications that do not require in-system-programming (ISP) function for firmwire upgrade, the Pm37LV512
offers a direct cost reduction path for Flash memory, i.e. Pm39LV512, without modifying the schematic and board
layout of system.
The Pm37LV512 is manufactured on pFLASH™’s advanced nonvolatile CMOS technology. The device is offered in
32-pin PLCC, VSOP and PDIP packages with 70ns access time.
Chingis Technology Corporation
1
Issue Date: April, 2006 Rev:1.5
Pm37LV512
CONNECTION DIAGRAMS
A12
A15
WE#
V
CC
NC
NC
NC
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
5
6
7
8
9
10
11
12
13
14
I/O1
4
3
2
1
32
31
30
29
28
27
26
25
24
23
22
21
A14
A13
A8
A9
A11
OE#
A10
CE#
I/O7
15
I/O2
16
GND
17
I/O3
18
I/O4
19
I/O5
20
I/O6
NC
NC
A15
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
V
CC
WE#
NC
A14
A13
A8
A9
A11
OE#
A10
CE#
I/O7
I/O6
I/O5
I/O4
I/O3
32-Pin PDIP
32-Pin PLCC
LOGIC SYMBOL
A11
A9
A8
A13
A14
NC
WE#
V
CC
NC
NC
A15
A12
A7
A6
A5
A4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
OE#
A10
CE#
I/O7
I/O6
I/O5
I/O4
I/O3
GND
I/O2
I/O1
I/O0
A0
A1
A2
A3
16
A0-A15
8
I/O0-I/O7
CE#
OE#
WE#
32-Pin VSOP
Chingis Technology Corporation
2
Issue Date: April, 2006 Rev: 1.5
Pm37LV512
PRODUCT ORDERING INFORMATION
Pm37LV512
-70
J
C
Temperature Range
C = Commercial (0°C to +70°C)
Package Type
J = 32-pin Plastic J-Leaded Chip Carrier (32J)
P = 32-pin Plastic DIP (32P)
V = 32-pin Thin Small Outline Package (32V)
Speed Option
Device Number
Pm37LV512 (512K bits)
Part Number
Pm37LV512-70JC
Pm37LV512-70PC
Pm37LV512-70VC
t
ACC
(ns)
Package
32J
Temperature Range
Commercial
(0
O
C to + 70
O
C)
Commercial
(0
O
C to + 70
O
C)
Commercial
(0
O
C to + 70
O
C)
70
32P
32V
Chingis Technology Corporation
3
Issue Date: April, 2006 Rev: 1.5
Pm37LV512
PIN DESCRIPTIONS
SYMBOL
A0 - A15
TYPE
INPUT
DESCRIPTION
Address Inputs: For memory addresses input. Addresses are internally
latched on the falling edge of WE# during a write cycle.
Chip Enable: CE# goes low activates the device's internal circuitries for
device operation. CE# goes high deselects the device and switches into
standby mode to reduce the power consumption.
Write Enable: Activate the device for write operation. WE# is active low.
Output Enable: Control the device's output buffers during a read cycle. OE#
is active low.
Data Inputs/Outputs: Input command/data during a write cycle or output data
during a read cycle. The I/O pins float to tri-state when OE# are disabled.
Device Power Supply
Ground
No Connection
CE#
INPUT
WE#
OE#
I/O0 - I/O7
V
CC
GND
NC
INPUT
INPUT
INPUT/
OUTPUT
Chingis Technology Corporation
4
Issue Date: April, 2006 Rev: 1.5
Pm37LV512
BLOCK DIAGRAM
I/O0-I/O7
I/O BUFFERS
WE#
CE#
OE#
COMMAND
REGISTER
CE,OE LOGIC
DATA
LATCH
SENSE
AMP
ADDRESS
LATCH
Y-DECODER
X-DECODER
Y-GATING
MEMORY
ARRAY
A0-A15
DEVICE OPERATION
READ OPERATION
The access of Pm37LV512 is similar as that of EPROM
or Flash Memory. To obtain data at the outputs, three
control functions must be satisfied:
• CE# is the chip enable and should be pulled low
( V
IL
).
• OE# is the output enable and should be pulled
low ( V
IL
).
• WE# is the write enable and should remains high
( V
IH
)
.
BYTE PROGRAMMING
The Pm37LV512 is programmed by using an external
EPROM programmer. The programming mode is acti-
vated by applying 12.0 Volt on OE# pin and V
IL
on CE#
pin. The byte program operation is completed by assert-
ing WE# to low for 20 µs. A chip erase operation is re-
quired prior to program due to a data “0” can not be pro-
grammed back to a “1” and only erase operation can con-
vert “0”s to “1”s. The entire chip can be programmed byte-
by-byte by using the byte program algorithmm. Refer to
Chart 1. Byte Programming Flowchart and Byte Program
Operations AC Waveforms.
Chingis Technology Corporation
CHIP ERASE
The entire memory array can be erased through a chip
erase operation on an external EPROM programmer. Pre-
program the “1”s cells in the device is not required prior
to chip erase operation. The chip erase operation is
activated by applying 12.0 Volt to OE# and A9 pins while
CE# pin is low. All other address and data pins are
“don’t care”. Chip erase is completed by asserting WE#
pin to low for 100 ms. The falling edge of WE# will start
the chip erase operation. The device will return back to
standby mode after the completion of chip erase. Refer
to Chart 2. Chip Erase Flowchart and Chip Erase
Operations AC Waveforms.
PRODUCT IDENTIFICATION
The hardware product identification mode can be used
by an EPROM programmer to identify the device and
manufacturer for selecting the right programming algo-
rithm for the device. The product identification mode is
activated by applying 12.0 Volt on A9 pin. For details,
please see Bus Operation Modes in Table 1.
5
Issue Date: April, 2006 Rev: 1.5
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