T80C5111
Low-pin-count 8-bit microcontroller with A/D converter
1. Description
The T80C5111 is a high performance ROM/OTP version
of the 80C51 8-bit microcontroller in Low Pin Count
package.
The T80C5111 retains all the features of the standard
80C51 with 4 Kbytes ROM/OTP program memory, 256
bytes of internal RAM, a 8-source , 4-level interrupt
system, an on-chip oscillator and two timer/counters.
The T80C5111 is dedicated for analog interfacing
applications. For this, it has an 10-bit, 8 channels A/D
converter and a five channels Programmable Counter
Array.
In addition, the T80C5111 has a Hardware Watchdog
Timer with its own low power oscillator, a versatile
serial
channel
that
facilitates
multiprocessor
communication (EUART) with an independent baud rate
generator, a SPI serial bus controller and a X2 speed
improvement mechanism. The X2 feature allows to keep
the same CPU power at a divided by two oscillator
frequency. The prescaler allows to decrease CPU and
peripherals clock frequency.
The fully static design of the T80C5111 allows to reduce
system power consumption by bringing the clock
frequency down to any value, even DC, without loss of
data.
The T80C5111 has 3 software-selectable modes of
reduced activity for further reduction in power
consumption. In the idle mode the CPU is frozen while
the peripherals are still operating. In the quiet mode, the
A/D converter only is operating. In the power-down
mode the RAM is saved and all other functions are
inoperative. Two oscillators source, crystal and RC,
provide a versatile power management.
The T80C5111 is proposed in low pin count packages.
Port 0 and Port 2 (address / data busses) are not available .
2. Features
•
80C51 Compatible
•
Three I/O ports
•
Two 16-bit timer/counters
•
256 bytes RAM
•
4 Kbytes ROM/OTP program memory with 64 bytes
encryption array and 3 security levels.
•
Dual system clock
•
Crystal or ceramic oscillator with hardware set
up (32 KHz or 33/40 MHz)
•
Internal RC oscillator (12 MHz)
•
Programmable prescaler
•
Active oscillator during reset defined by hardware
set up
•
Timer 0 subclock mode for Real Time Clock.
•
Programmable counter array with High speed output,
Compare / Capture, Pulse Width Modulation and
Watchdog timer capabilities
•
High-Speed Architecture
•
33MHz @ 5V (66 MHz equivalent)
•
20MHz @ 3V (40 MHz equivalent)
•
X2 Speed Improvement capability (6 clocks/
machine cycle)
•
10-bit, 8 channels A/D converter
•
Interrupt Structure with:
•
8 Interrupt sources,
•
4 interrupt priority levels
•
Power Control modes:
•
Idle mode
•
Power-down mode
•
Power-off Flag, Power fail detect, Power on Reset
•
Power supply: 2.7 to 5.5V
•
Voltage reference for A/D & external analog
•
Hardware Watchdog Timer with integrated low
power oscillator (20µA).
•
Programmable I/O mode: standard C51, input only,
push-pull, open drain.
•
Asynchronous port reset, Power On Reset, Power
fail Detect
•
Full duplex Enhanced UART with baud rate generator
•
SPI, master/slave mode
•
Temperature ranges: Commercial (0 to 70
o
C) and
Industrial (-40 to 85
o
C)
Rev. B - November 10, 2000
1
Preliminary
T80C5111
•
Package: SSOP16, SO24, DIL24, (SSOP24, SO20, under evaluation)
3. Block Diagram
CEX0-4
ECI
MISO
MOSI
SPSCK
SS
(3) (3) (3) (3)
RxD
TxD
Vcc
Vss
(2) (2)
(2)
XTAL1
(2)
XTAL2
Xtal
Osc
(1) (1)
EUART
BRG
RAM
256
x8
ROM /OTP
PCA
SPI
4 K *8
Watch
Dog
RC
Osc
C51
CORE
RC
Osc
IB-bus
CPU
Timer 0
Timer 1
INT
Ctrl
Vref
generator
Parallel I/O Ports
A/D
Converter
Port 1 Port 3 Port 4
(2)
RST/Vpp
(2) (3)
T0
T1
(2) (3)
(3)
AIN0-7
INT0
INT1
P1
Vref
P3
P4
(1): Alternate function of Port 1
(2): Alternate function of Port 3
(3): Alternate function of Port 4
2
Rev. B - November 10, 2000
Preliminary
T80C5111
4. alias SFR Mapping
The Special Function Registers (SFRs) of the T80C5111 belongs to the following categories:
•
•
•
•
•
C51 core registers: ACC, B, DPH, DPL, PSW, SP, AUXR1
I/O port registers: P1, P3, P4, P1M1, P1M2, P3M1, P3M2, P4M1, P4M2
Timer registers: TCON, TH0, TH1, TMOD, TL0, TL1
Serial I/O port registers: SADDR, SADEN, SBUF, SCON, BRL, BDRCON
Power and clock control registers: CKCON0, CKCON1, OSCCON, CKSEL, PCON, CKRL
•
Interrupt system registers: IE, IE1, IPL0, IPL1, IPH0, IPH1
•
WatchDog Timer: WDTRST, WDTPRG
•
SPI: SPCON, SPSTA, SPDAT
•
PCA: CCAP0L, CCAP1L, CCAP2L, CCAP3L, CCAP4L, CCAP0H, CCAP1H, CCAP2H, CCAP3H,
CCAP4H, CCAPM0, CCAPM1, CCAPM2, CCAPM3, CCAPM4, CL, CH, CMOD, CCON
•
ADC: ADCCON, ADCCLK, ADCDATH, ADCDATL, ADCF
Table 1. SFR Addresses and Reset Values
0/8
F8h
F0h
E8h
E0h
D8h
D0h
C8h
C0h
B8h
B0h
A8h
A0h
98h
90h
88h
80h
0/8
SCON
0000 0000
P1
1111 1111
TCON
0000 0000
TMOD
0000 0000
SP
0000 0111
1/9
TL0
0000 0000
DPL
0000 0000
2/A
TL1
0000 0000
DPH
0000 0000
3/B
4/C
TH0
0000 0000
TH1
0000 0000
CKSEL
OSCCON
XXXX XXXC XXXX XXCC
5/D
6/E
SBUF
XXXX XXXX
P4
1111 1111
IPL0
0000 0000
P3
1111 1111
IE0
0000 0000
SADEN
0000 0000
IE1
0000 0000
SADDR
0000 0000
AUXR1
XXXXXXX0
BRL
0000 0000
BDRCON
0000 0000
CKRL
1111 1111
CKCON0
X000X000
PCON
00X1 0000
7/F
WDRST
0000 0000
IPL1
0000 0000
IPH1
0000 0000
IPH0
X000 0000
SPCON
0001 0100
SPSTA
SPDAT
XXXXXXXX XXXX XXXX
ACC
0000 0000
CCON
00X0 0000
PSW
0000 0000
CMOD
X000 0000
B
0000 0000
CL
0000 0000
1/9
CH
0000 0000
2/A
3/B
4/C
5/D
6/E
7/F
FFh
F7h
CONF
1111 111X
EFh
E7h
CCAPM4
X000 0000
P4M1
0000 0000
DFh
D7h
CFh
C7h
BFh
B7h
CCAP0H
CCAP1H
CCAP2H
CCAP3H
CCAP4H
XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX
ADCLK
0000 0000
ADCON
0000 0000
ADDL
XXXXXX00
ADDH
0000 0000
ADCF
0000 0000
CCAP0L
CCAP1L
CCAP2L
CCAP3L
CCAP4L
XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX
P1M2
0000 0000
CCAPM0
00XX X000
CCAPM1
X000 0000
P3M2
0000 0000
CCAPM2
X000 0000
P1M1
0000 0000
P4M2
0000 0000
CCAPM3
X000 0000
P3M1
0000 0000
CKCON1
AFh
XXXX XXX0
WDTPRG
0000 0000
A7h
9Fh
97h
8Fh
87h
Notes:
"C", value defined by the configuration byte, see Section “Configuration byte”, page 10
Rev. B - November 10, 2000
3
Preliminary
T80C5111
5. Pin Configuration
P4.4/MISO/AIN4
P4.5/MOSI/AIN5
P4.6/SPSCK/AIN6
P4.7/AIN7
VREF
VSS
VCC
P3.6/RST/VPP
P3.5/XTAL2
P3.4/XTAL1
P1.7/CEX4
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
P4.3/INT1/AIN3
P4.2/SS/AIN2
P4.1/AIN1/T1
P4.0/AIN0
P4.4/MISO/AIN4
P4.5/MOSI/AIN5
P4.6/SPSCK/AIN6
VREF
VSS
AVSS
AVCC
VCC
P3.6/RST/VPP
P3.5/XTAL2
P3.4/XTAL1
P1.6/CEX3
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
P4.3/INT1/AIN3
P4.2/SS/AIN2
P4.1/AIN1/T1
P4.0/AIN0
SO24
DIL24
20
19
18
17
16
15
14
13
P3.0/RxD
P3.1/TxD
P1.2/ECI
P1.3/CEX0
P1.4/CEX1
P1.5/CEX2
P3.2/INT0
SSOP24*
20
19
18
17
16
15
14
13
P3.0/RxD
P3.1/TxD
P1.2/ECI
P1.3/CEX0
P1.4/CEX1
P1.5/CEX2
P3.2/INT0
P1.6/CEX3
P3.3/T0
P3.3/T0
P4.4/AIN4
P4.6/AIN6
VREF
VSS
VCC
P3.6/RST/VPP
P3.5/XTAL2
P3.4/XTAL1
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
P4.1/AIN1/T1
P4.0/AIN0
P3.0/RxD
P3.1/TxD
P1.3/CEX0
P1.4/CEX1
P3.2/INT0
P4.4/MISO/AIN4
P4.5/MOSI/AIN5
P4.6/SPSCK/AIN6
VREF
VSS
VCC
P3.6/RST/VPP
P3.5/XTAL2
P3.4/XTAL1
P1.6/CEX3
1
2
3
4
5
6
7
8
9
10
20
19
18
27
P4.2/SS/AIN2
P4.1/AIN1/T1
P4.0/AIN0
P3.0/RxD
P3.1/TxD
P1.3/CEX0
P1.4/CEX1
P1.5/CEX2
P3.2/INT0
SSOP16
SO20*
P3.3/T0
26
15
14
13
12
11
P3.3/T0
* Under evaluation
MNEMONIC
V
SS
V
CC
VREF
P1.2-P1.7
TYPE
I
I
I/O
I/O
Ground:
0V reference
NAME AND FUNCTION
Power Supply:
This is the power supply voltage for normal, idle and power-
down operation.
VREF :
A/D converter positive reference input, output of the internal voltage
reference
Port 1: Port 1 is an 6-bit programmable I/O port .See Section 9, page 21 for a
description of I/O ports.
Alternate functions for Port 1 include:
I/O
I/O
I/O
I/O
I/O
I/O
ECI (P1.2):
External Clock for the PCA
CEX0 (P1.3):
Capture/Compare External I/O for PCA module 0
CEX1 (P1.4):
Capture/Compare External I/O for PCA module 1
CEX2 (P1.5):
Capture/Compare External I/O for PCA module 2
CEX3 (P1.6):
Capture/Compare External I/O for PCA module 3
CEX4 (P1.7):
Capture/Compare External I/O for PCA module 4
4
Rev. B - November 10, 2000
Preliminary
T80C5111
P3.0-P3.6
I/O
Port 3: Port 3 is an 7-bit programmable I/O port with internal pull-ups. See
Section 9, page 21 for a description of I/O ports.
Port 3 also serves the special features of the 80C51 family, as listed below.
I/O
I/O
I/O
I/O
I/O
I/O
RXD (P3.0):
Serial input port
TXD (P3.1):
Serial output port
INT0 (P3.2):
External interrupt 0
T0 (P3.3):
Timer 0 external input
XTAL1 (P3.4):
Input to the inverting oscillator amplifier and input to the internal
clock generator circuits, selected by hardware set up
a
XTAL2 (P3.5):
Output from the inverting oscillator amplifier, selected by
hardware set up
RST/Vpp (P3.6 is not implemented on first version):
Reset/Programming
Supply Voltage:
A low on this pin for two machine cycles while the oscillator is running, resets
the device. An internal diffused resistor to V
cc
permits a power-on reset using
only the internal ( selected by hardware set up) or an external capacitor to V
SS.
This pin also receives the 12V programming pulse which will start the EPROM
programming and the manufacturer test modes.
Port 4:
Port 4 is an 8-bit programmable I/O port with internal pull-ups. See
Section 9, page 21 for a description of I/O ports.
Port 4 is also the input port of the Analog to digital converter
AIN0 (P4.0):
A/D converter input 0
AIN1 (P4.1):
A/D converter input 1
T1:
Timer 1 external input
AIN2 (P4.2):
A/D converter input 2
SS:
Slave select input of the SPI controller
AIN3 (P4.3):
A/D converter input 3
INT1:
External interrupt 1
AIN4 (P4.4):
A/D converter input 4
MISO:
Master IN, Slave OUT of the SPI controller
AIN5 (P4.5):
A/D converter input 5
MOSI:
Master OUT, Slave IN of the SPI controllers
AIN6 (P4.6):
A/D converter input 6
SPSCK:
Clock I/O of the SPI controlle
AIN7 (P4.7):
A/D converter input 7
I
P4.0-P4.7
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
a. Hardware set up :
+Configuration bits programmed with the code for ROM version
+Configuration bits for EPROM version
Rev. B - November 10, 2000
5
Preliminary
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