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TSC80C31-L20ICR/883

Description
GT 37C 37#16 SKT RECP
File Size279KB,19 Pages
ManufacturerTEMIC
Websitehttp://www.temic.de/
Download Datasheet View All

TSC80C31-L20ICR/883 Overview

GT 37C 37#16 SKT RECP

versions of the 8051 NMOS single chip 8 bit
µC.
The fully static design of the TSC80C31/80C51 allows to
reduce system power consumption by bringing the clock
frequency down to any value, even DC, without loss of
data.
The TSC80C31/80C51 retains all the features of the 8051
: 4 K bytes of ROM ; 128 bytes of RAM ; 32 I/O lines ;
two 16 bit timers ; a 5-source, 2-level interrupt structure
; a full duplex serial port ; and on-chip oscillator and clock
circuits.
software-selectable modes of reduced activity for further
reduction in power consumption. In the Idle Mode the
CPU is frozen while the RAM, the timers, the serial port,
and the interrupt system continue to function. In the
Power Down Mode the RAM is saved and all other
functions are inoperative.
The TSC80C31/80C51 is manufactured using SCMOS
process which allows them to run from 0 up to 44 MHz
with VCC = 5 V. The TSC80C31/80C51 is also available
at 20 MHz with 2.7 V < Vcc < 5.5 V.
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TSC80C31/80C51-L16 : Low power version
Vcc : 2.7–5.5 V Freq : 0–16 MHz
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TSC80C31/80C51-L20 : Low power version
Vcc : 2.7–5.5 V Freq : 0–20 MHz
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TSC80C31/80C51-12 : 0 to 12 MHz
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TSC80C31/80C51-20 : 0 to 20 MHz
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TSC80C31/80C51-25 : 0 to 25 MHz
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TSC80C31/80C51-30 : 0 to 30 MHz
TSC80C31/80C51-36 : 0 to 36 MHz
TSC80C31/80C51-40 : 0 to 40 MHz
TSC80C31/80C51-44 : 0 to 44 MHz*
* Commercial and Industrial temperature range only. For other speed
and range please consult your sale office.
Features
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Power control modes
128 bytes of RAM
4 K bytes of ROM (TSC80C31/80C51)
32 programmable I/O lines
Two 16 bit timer/counter
64 K program memory space
64 K data memory space
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Fully static design
0.8
µm
CMOS process
Boolean processor
5 interrupt sources
Programmable serial port
Temperature range : commercial, industrial, automotive and
military
Optional
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Secret ROM : Encryption
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Secret TAG : Identification number
MATRA MHS
Rev. E (14 Jan.97)
1
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