Freescale Semiconductor, Inc.
PREFACE
The complete documentation package for the MC68330 consists of the
MC68330
Integrated CPU32 Processor User’s Manual
(MC68330UM/AD) and the
MC68330
Integrated CPU32 Processor Technical Summary
(MC68330UM/D).
The
MC68330 Integrated CPU32 Processor User’s Manual
describes the programming,
capabilities, registers, and operation of the MC68330. The
MC68330 Integrated CPU32
Processor Technical Summary
provides a description of the MC68330 capabilities and
detailed electrical specifications.
This user’s manual is organized as follows:
Section
Section
Section
Section
Section
Section
Section
Section
Section
1
2
3
4
5
6
7
8
9
Device Overview
Signal Descriptions
Bus Operation
System Integration Module
CPU32
IEEE 1149.1 Test Access Port
Applications
Electrical Characteristics
Ordering Information and Mechanical Data
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MC68330 USER’S MANUAL
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TABLE OF CONTENTS
Paragraph
Number
Title
Section 1
Device Overview
Page
Number
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1.1
1.2
1.2.1
1.2.2
1.2.3
1.2.4
Central Processor Unit .................................................................................... 1-2
System Integration Module.............................................................................1-2
System Configuration and Protection Submodule.....................................1-2
Clock Synthesizer.............................................................................................1-3
Chip Selects ......................................................................................................1-3
External Bus Interface......................................................................................1-3
Section 2
Signal Descriptions
2.1
2.2
2.2.1
2.2.2
2.3
2.4
2.5
2.6
2.7
2.7.1
2.7.2
2.7.3
2.7.4
2.7.5
2.7.6
2.8
2.8.1
2.8.2
2.8.3
2.8.4
2.8.5
2.9
2.9.1
2.9.2
2.9.3
2.10
MOTOROLA
Signal Index.......................................................................................................2-1
Address Bus.......................................................................................................2-1
Address Bus (A23—A0)...................................................................................2-1
Address Bus (A31—A24) ................................................................................2-1
Data Bus (D15—D0) ........................................................................................2-4
Function Codes (FC3—FC0)......................................................................... 2-4
Chip Selects (CS3—CS0)............................................................................... 2-4
Interrupt Request Level (IRQ7,
IRQ6, IRQ5, IRQ3)
................................ 2-5
Bus Control Signals .........................................................................................2-5
Data and Size Acknowledge (DSACK1,
DSACK0)..................................
2-5
Autovector (AVEC)............................................................................................2-5
Address Strobe (AS)........................................................................................2-5
Data Strobe (DS)...............................................................................................2-5
Transfer Size (SIZ1, SIZ0) ..............................................................................2-6
Read/Write (R/W)...............................................................................................2-6
Bus Arbitration Signals....................................................................................2-6
Bus Request (BR)..............................................................................................2-6
Bus Grant (BG)...................................................................................................2-6
Bus Grant Acknowledge (BGACK).................................................................2-6
Read-Modify-Write Cycle (RMC).....................................................................2-6
Byte Write Enable (UWE,
LWE)......................................................................2-7
Exception Control Signals ..............................................................................2-7
Reset (RESET)...................................................................................................2-7
Halt (HALT)........................................................................................................2-7
Bus Error (BERR)...............................................................................................2-7
Clock Signals ....................................................................................................2-7
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TABLE OF CONTENTS (Continued)
Paragraph
Number
2.10.1
2.10.2
2.10.3
2.10.4
2.11
2.11.1
2.11.2
2.11.3
2.11.4
2.12
2.12.1
2.12.2
2.12.3
2.12.4
2.13
2.14
2.15
Title
Page
Number
System Clock (CLKOUT).................................................................................2-7
Crystal Oscillator (EXTAL, XTAL)...................................................................2-8
External Filter Capacitor (XFC) ......................................................................2-8
Clock Mode Select (MODCK).........................................................................2-8
Instrumentation and Emulation Signals .......................................................2-8
Instruction Fetch (IFETCH)..............................................................................2-8
Instruction Pipe (IPIPE)...................................................................................2-8
Breakpoint (BKPT)............................................................................................2-8
Freeze (FREEZE)..............................................................................................2-8
Test Signals.......................................................................................................2-9
Test Clock (TCK)...............................................................................................2-9
Test Mode Select (TMS).................................................................................. 2-9
Test Data In (TDI)..............................................................................................2-9
Test Data Out (TDO).........................................................................................2-9
Synthesizer Power (VCCSYN) ......................................................................2-9
System Power and Gound (VCC and GND)................................................2-9
Signal Summary...............................................................................................2-9
Section 3
Bus Operation
3.1
3.1.1
3.1.2
3.1.3
3.1.4
3.1.5
3.1.6
3.1.7
3.1.8
3.1.8.1
3.1.8.2
3.1.8.3
3.2
3.2.1
3.2.2
3.2.3
3.2.3.1
3.2.3.2
3.2.3.3
3.2.3.4
3.2.3.5
3.2.3.6
3.2.3.7
3.2.4
Bus Transfer Signals........................................................................................3-1
Bus Control Signals .........................................................................................3-2
Function Codes.................................................................................................3-3
Address Bus (A31—A0)...................................................................................3-3
Address Strobe (AS)........................................................................................3-3
Data Bus (D15—D0) ........................................................................................3-4
Data Strobe (DS)...............................................................................................3-4
Byte Write Enable (UWE,
LWE).......................................................................3-4
Bus Cycle Termination Signals......................................................................3-4
Data Transfer and Size Acknowledge Signals (DSACK1 and
DSACK0)
3-4
Bus Error (BERR)...............................................................................................3-5
Autovector (AVEC)............................................................................................3-5
Data Transfer Mechanism...............................................................................3-5
Dynamic Bus Sizing.........................................................................................3-5
Misaligned Operands.......................................................................................3-7
Operand Transfer Cases.................................................................................3-8
Byte Operand to 8-Bit Port, Even (A0=0)......................................................3-8
Byte Operand to 16-Bit Port, Even (A0=0)....................................................3-8
Byte Operand to 16-Bit Port, Odd (A0=1) .....................................................3-9
Word Operand to 8-Bit Port, Aligned.............................................................3-9
Word Operand to 16-Bit Port, Aligned........................................................ 3-10
Long-Word Operand to 8-Bit Port, Aligned ............................................... 3-10
Long-Word Operand to 16-Bit Port, Aligned............................................. 3-12
Bus Operation................................................................................................. 3-14
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TABLE OF CONTENTS (Continued)
Paragraph
Number
3.2.5
3.2.6
3.3
3.3.1
3.3.2
3.3.3
3.4
3.4.1
3.4.2
3.4.3
3.4.4
3.4.4.1
3.4.4.2
3.4.4.3
3.5
3.5.1
3.5.2
3.5.3
3.5.4
3.6
3.6.1
3.6.2
3.6.3
3.6.4
3.6.5
3.7
Title
Page
Number
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Synchronous Operation with
DSACKx
...................................................... 3-14
Fast-Termination Cycles............................................................................... 3-15
Data Transfer Cycles..................................................................................... 3-16
Read Cycle...................................................................................................... 3-17
Write Cycle...................................................................................................... 3-18
Read-Modify-Write Cycle.............................................................................. 3-19
CPU Space Cycles........................................................................................ 3-22
Breakpoint Acknowledge Cycle.................................................................. 3-22
LPSTOP Broadcast Cycle............................................................................ 3-26
Module Base Address Register Access..................................................... 3-27
Interrupt Acknowledge Bus Cycles............................................................. 3-27
Interrupt Acknowledge Cycle — Terminated Normally........................... 3-27
Autovector Interrupt Acknowledge Cycle .................................................. 3-30
Spurious Interrupt Cycle............................................................................... 3-32
Bus Exception Control Cycles..................................................................... 3-33
Bus Errors........................................................................................................ 3-35
Retry Operation .............................................................................................. 3-37
Halt Operation ................................................................................................ 3-38
Double Bus Fault ........................................................................................... 3-40
Bus Arbitration................................................................................................ 3-40
Bus Request.................................................................................................... 3-43
Bus Grant......................................................................................................... 3-43
Bus Grant Acknowledge............................................................................... 3-43
Bus Arbitration Control.................................................................................. 3-43
Show Cycles................................................................................................... 3-45
Reset Operation ............................................................................................. 3-47
Section 4
System Integration Module
4.1
4.2
4.2.1
4.2.2
4.2.2.1
4.2.2.2
4.2.2.3
4.2.2.4
4.2.2.5
4.2.2.6
4.2.2.6.1
4.2.2.6.2
4.2.2.7
4.2.3
4.2.3.1
4.2.3.2
Module Overview..............................................................................................4-1
Module Operation.............................................................................................4-2
Module Base Address Register......................................................................4-2
System Configuration and Protection Function ..........................................4-3
System Configuration ......................................................................................4-5
Internal Bus Monitor .........................................................................................4-5
Double Bus Fault Monitor................................................................................ 4-5
Spurious Interrupt Monitor ..............................................................................4-5
Software Watchdog..........................................................................................4-6
Periodic Interrupt Timer ...................................................................................4-6
Periodic Timer Period Calculation.................................................................4-7
Using the Periodic Timer as a Real-Time Clock .........................................4-8
Simultaneous Interrupts by Sources in the SIM40.....................................4-8
Clock Synthesizer.............................................................................................4-8
Phase Comparator and Filter ...................................................................... 4-11
Frequency Divider ......................................................................................... 4-11
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TABLE OF CONTENTS (Continued)
Paragraph
Number
4.2.3.3
4.2.4
4.2.4.1
4.2.4.2
4.2.5
4.2.5.1
4.2.5.2
4.2.6
4.2.7
4.3
4.3.1
4.3.2
4.3.2.1
4.3.2.2
4.3.2.3
4.3.2.4
4.3.2.5
4.3.2.6
4.3.2.7
4.3.2.8
4.3.3
4.3.4.
4.3.4.1
4.3.4.2
4.3.4.3
4.3.5
4.3.5.1
4.3.5.2
4.3.5.3
4.3.5.4
4.3.5.5
4.3.5.6
4.3.5.7
Title
Page
Number
Clock Control.................................................................................................. 4-12
Chip-Select Function .................................................................................... 4-12
Programmable Features............................................................................... 4-13
Global Chip-Select Operation..................................................................... 4-13
External Bus Interface................................................................................... 4-14
Port A................................................................................................................ 4-14
Port B................................................................................................................ 4-14
Low-Power Stop ............................................................................................ 4-15
Freeze.............................................................................................................. 4-15
Programmer's Model..................................................................................... 4-16
Module Base Address Register................................................................... 4-17
System Configuration and Protection Registers...................................... 4-18
Module Configuration Register (MCR)....................................................... 4-18
Autovector Register (AVR)............................................................................ 4-20
Reset Status Register (RSR)........................................................................ 4-20
Software Interrupt Vector Register (SWIV)................................................ 4-21
System Protection Control Register (SYPCR).......................................... 4-21
Periodic Interrupt Control Register (PICR) ................................................ 4-23
Periodic Interrupt Timer Register (PITR).................................................... 4-24
Software Service Register (SWSR) ........................................................... 4-24
Clock Synthesizer Control Register (SYNCR) ......................................... 4-25
Chip-Select Registers................................................................................... 4-26
Base Address Registers ............................................................................... 4-26
Address Mask Registers............................................................................... 4-27
Chip-Select Registers Programming Example ........................................ 4-29
External Bus Interface Control..................................................................... 4-29
Port A Pin Assignment Register 1 (PPARA1)............................................ 4-29
Port A Pin Assignment Register 2 (PPARA2)............................................ 4-30
Port A Data Direction Register (DDRA)...................................................... 4-30
Port A Data Register (PORTA)..................................................................... 4-30
Port B Pin Assignment Register (PPARB) ................................................. 4-31
Port B Data Direction Register (DDRB)...................................................... 4-31
Port B Data Register (PORTB, PORTB1) ................................................... 4-31
Section 5
CPU32
5.1
5.1.1
5.1.2
5.1.3
5.1.4
5.1.5
5.1.6
5.1.7
5.1.7.1
5.1.7.2
vi
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Overview.............................................................................................................5-1
Features..............................................................................................................5-2
Virtual Memory ..................................................................................................5-2
Loop Mode Instruction Execution ..................................................................5-3
Vector Base Register........................................................................................5-4
Exception Handling..........................................................................................5-4
Addressing Modes............................................................................................5-5
Instruction Set....................................................................................................5-5
Table Lookup and Interpolate Instructions...................................................5-5
Low-Power Stop Instruction............................................................................5-7
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