LSU406
LOW NOISE, LOW DRIFT
MONOLITHIC DUAL
N-CHANNEL JFET
Linear Systems replaces discontinued Siliconix U406
The LSU406 is a Low Noise, Low Drift, Monolithic Dual N-Channel JFET
The LSU406 is a high-performance monolithic dual
JFET featuring extremely low noise, tight offset voltage
and low drift over temperature specifications, and is
targeted for use in a wide range of precision
instrumentation applications. The LSU406 features a 5-
mV offset and 10-µV/°C drift. The LSU406 is a direct
replacement for discontinued Siliconix LSU406.
The 8 Pin P-DIP and 8 Pin SOIC provide ease of
manufacturing, and the symmetrical pinout prevents
improper orientation.
(See Packaging Information).
FEATURES
LOW DRIFT
LOW NOISE
LOW PINCHOFF
ABSOLUTE MAXIMUM RATINGS
@ 25°C (unless otherwise noted)
| V
GS1‐2
/ T| = 10µV/°C TYP.
e
n
= 6nV/Hz @ 10Hz TYP.
V
p
= 2.5V TYP.
LSU406 Applications:
Wideband Differential Amps
High-Speed,Temp-Compensated Single-Ended
Input Amps
High-Speed Comparators
Impedance Converters and vibrations detectors.
Maximum Temperatures
Storage Temperature
‐65°C to +150°C
Operating Junction Temperature
+150°C
Maximum Voltage and Current for Each Transistor – Note 1
‐V
GSS
Gate Voltage to Drain or Source
50V
‐V
DSO
Drain to Source Voltage
50V
‐I
G(f)
Gate Forward Current
10mA
Maximum Power Dissipation
Device Dissipation @ Free Air – Total 300mW
MATCHING CHARACTERISTICS @ 25°C UNLESS OTHERWISE NOTED
SYMBOL
CHARACTERISTICS VALUE UNITS CONDITIONS
| V
GS1‐2
/ T| max.
DRIFT VS.
80
µV/°C V
DG
=10V, I
D
=200µA
TEMPERATURE
T
A
=‐55°C to +125°C
| V
GS1‐2
| max.
OFFSET VOLTAGE
40
mV
V
DG
=10V, I
D
=200µA
TYP.
60
‐‐
‐‐
‐‐
0.6
‐‐
1
‐‐
‐‐
‐4
‐‐
‐‐
5
‐‐
0.2
‐‐
‐‐
20
‐‐
‐‐
MAX.
‐‐
‐‐
7000
2000
3
10
5
‐2.5
‐2.3
‐15
‐10
100
5
20
2
‐‐
0.5
‐‐
8
1.5
UNITS
V
V
µmho
µmho
%
mA
%
V
V
pA
nA
pA
pA
µmho
µmho
dB
dB
nV/√Hz
pF
pF
CONDITIONS
V
DS
= 0 I
D
=1nA
I
G
= 1nA I
D
= 0 I
S
= 0
V
DG
= 10V V
GS
= 0V f = 1kHz
V
DG
= 15V I
D
= 200µA f = 1kHz
V
DG
= 10V V
GS
= 0V
V
DS
= 15V I
D
= 1nA
V
DS
=15V I
D
=200µA
V
DG
= 15V I
D
= 200µA
T
A
= +125°C
V
DS
=0
V
DG
= 15V T
A
= +125°C
V
DG
= 10V V
GS
= 0V
V
DG
= 15V I
D
= 500µA
V
DS
= 10 to 20V I
D
=30µA
V
DS
= 15V V
GS
= 0V R
G
= 10M
f= 100Hz NBW= 6Hz
V
DS
=15V I
D
=200µA f=10Hz NBW=1Hz
V
DS
= 15V I
D
= 200µA f= 1MHz
ELECTRICAL CHARACTERISTICS @ 25°C (unless otherwise noted)
SYMBOL
CHARACTERISTICS
MIN.
BV
GSS
Breakdown Voltage
50
BV
GGO
Gate‐To‐Gate Breakdown
±50
TRANSCONDUCTANCE
Y
fSS
Full Conduction
2000
Y
fS
Typical Operation
1000
|Y
FS1‐2
/ Y
FS
|
Mismatch
‐‐
DRAIN CURRENT
I
DSS
Full Conduction
0.5
|I
DSS1‐2
/ I
DSS
|
Mismatch at Full Conduction
‐‐
GATE VOLTAGE
V
GS
(off) or V
p
Pinchoff voltage
‐0.5
V
GS
(on)
Operating Range
‐‐
GATE CURRENT
‐I
G
max.
Operating
‐‐
‐I
G
max.
High Temperature
‐‐
‐I
GSS
max.
At Full Conduction
‐‐
‐I
GSS
max.
High Temperature
5
OUTPUT CONDUCTANCE
Y
OSS
Full Conduction
‐‐
Y
OS
Operating
‐‐
COMMON MODE REJECTION
CMR
‐20 log | V
GS1‐2
/ V
DS
|
95
NOISE
NF
Figure
‐‐
e
n
Voltage
‐‐
CAPACITANCE
C
ISS
Input
‐‐
C
RSS
Reverse Transfer
‐‐
Click To Buy
Note 1 – These ratings are limiting values above which the serviceability of any semiconductor may be impaired
PDIP / SOIC (Top View)
Micross Components Europe
Available Packages:
LSU406 in PDIP / SOIC
LSU406 available as bare die
Please contact
Micross
for full package and die dimensions
Tel: +44 1603 788967
Email:
chipcomponents@micross.com
Web:
http://www.micross.com/distribution
Information furnished by Linear Integrated Systems and Micross Components is believed to be accurate and reliable. However, no responsibility is assumed for its use; nor for any infringement of patents or
other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Linear Integrated Systems.
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