A3PN030-ZFQNG48 datasheet, PDF

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A3PN030-ZFQNG48: DescriptionField Programmable Gate Array, 768 CLBs, 30000 Gates, 256-Cell, CMOS, 6 X 6 MM, 0.90 HEIGHT, 0.40 MM PITCH, ROHS COMPLIANT, QFN-48; CategoryProgrammable logic devices Programmable logic; File Size3MB，92 Pages; ManufacturerMicrosemi; Websitehttps://www.microsemi.com; Environmental Compliance

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A3PN030-ZFQNG48 Overview

Field Programmable Gate Array, 768 CLBs, 30000 Gates, 256-Cell, CMOS, 6 X 6 MM, 0.90 HEIGHT, 0.40 MM PITCH, ROHS COMPLIANT, QFN-48

A3PN030-ZFQNG48 Parametric

Parameter Name	Attribute value
Is it Rohs certified?	conform to
Maker	Microsemi
package instruction	HQCCN, LCC48,.24SQ,16
Reach Compliance Code	compliant
JESD-30 code	S-XQCC-N48
length	6 mm
Configurable number of logic blocks	768
Equivalent number of gates	30000
Number of entries	34
Number of logical units	256
Output times	34
Number of terminals	48
Maximum operating temperature	70 °C
Minimum operating temperature	-20 °C
organize	768 CLBS, 30000 GATES
Package body material	UNSPECIFIED
encapsulated code	HQCCN
Encapsulate equivalent code	LCC48,.24SQ,16
Package shape	SQUARE
Package form	CHIP CARRIER, HEAT SINK/SLUG
Peak Reflow Temperature (Celsius)	260
power supply	1.5,1.5/3.3 V
Programmable logic type	FIELD PROGRAMMABLE GATE ARRAY
Certification status	Not Qualified
Maximum supply voltage	1.575 V
Minimum supply voltage	1.425 V
Nominal supply voltage	1.5 V
surface mount	YES
technology	CMOS
Temperature level	OTHER
Terminal form	NO LEAD
Terminal pitch	0.4 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	30
width	6 mm

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Advance v0.4

ProASIC 3 nano Flash FPGAs

Features and Benefits

Wide Range of Features

• 10 k to 250 k System Gates

• Up to 36 kbits of True Dual-Port SRAM

• Up to 71 User I/Os

Advanced I/Os

• 1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation

• Bank-Selectable I/O Voltages—up to 4 Banks per Chip

• Single-Ended I/O Standards: LVTTL, LVCMOS 3.3 V /

2.5 V / 1.8 V / 1.5 V

• Wide Range Power Supply Voltage Support per JESD8-B,

Allowing I/Os to Operate from 2.7 V to 3.6 V

• I/O Registers on Input, Output, and Enable Paths

• Selectable Schmitt Trigger Inputs

• Hot-Swappable and Cold-Sparing I/Os

• Programmable Output Slew Rate

†

and Drive Strength

• Weak Pull-Up/-Down

• IEEE 1149.1 (JTAG) Boundary Scan Test

• Pin-Compatible Packages across the ProASIC3 Family

†

• Up to Six CCC Blocks, One with an Integrated PLL

• Configurable Phase Shift, Multiply/Divide, Delay

Capabilities and External Feedback

• Wide Input Frequency Range (1.5 MHz to 350 MHz)

Reprogrammable Flash Technology

•

130-nm, 7-Layer Metal (6 Copper), Flash-Based CMOS Process

Live at Power-Up (LAPU) Level 0 Support

Single-Chip Solution

Retains Programmed Design when Powered Off

High Performance

• 350 MHz System Performance

In-System Programming (ISP) and Security

• Secure ISP Using On-Chip 128-Bit Advanced Encryption

Standard (AES) Decryption via JTAG (IEEE 1532–compliant)

†

• FlashLock

to Secure FPGA Contents

Clock Conditioning Circuit (CCC) and PLL

Low Power

•

Low-Power ProASIC3 nano Products

1.5 V Core Voltage for Low Power

Support for 1.5 V-Only Systems

Low-Impedance Flash Switches

Embedded Memory

• 1 kbit of FlashROM User Nonvolatile Memory

• SRAMs and FIFOs with Variable-Aspect-Ratio 4,608-Bit RAM

Blocks (×1, ×2, ×4, ×9, and ×18 organizations)

†

• True Dual-Port SRAM (except ×18 organization)

†

High-Performance Routing Hierarchy

• Segmented, Hierarchical Routing and Clock Structure

Enhanced Commercial Temperature Range

• –20°C to +70°C

Table 1 •

ProASIC3 nano Devices

System Gates

Typical Equivalent Macrocells

VersaTiles (D-flip-flops)

RAM kbits (1,024 bits)

4,608-Bit

Blocks

A3PN010

10 k

260

–

QN48

A3PN015

15 k

128

384

–

QN68

A3PN020

20 k

172

520

–

QN68

A3PN030

30 k

256

768

–

QN48, QN68

VQ100

A3PN060

60 k

512

1,536

Yes

A3PN125

125 k

1,024

3,072

Yes

A3PN250

250 k

2,048

6,144

Yes

FlashROM Bits

Secure (AES) ISP

Integrated PLL in CCCs

VersaNet Globals

I/O Banks

Maximum User I/Os (packaged device)

Maximum User I/Os (Known Good Die)

Package Pins

QFN

VQFP

VQ100

Notes:

1. A3PN030 is available in the Z feature grade only and offers package compatibility with the lower density nano devices. Refer to

"ProASIC3 nano Ordering Information" on page III.

2. A3PN030 and smaller devices do not support this feature.

3. For higher densities and support of additional features, refer to the

ProASIC3

and

ProASIC3E

handbooks.

† A3PN030 and smaller devices do not support this feature.

January 2009

1 – ProASIC3 nano Device Overview

General Description

ProASIC3, the third-generation family of Actel flash FPGAs, offers performance, density, and

features beyond those of the ProASIC

PLUS®

family. Nonvolatile flash technology gives ProASIC3

nano devices the advantage of being a secure, low-power, single-chip solution that is live at power-

up (LAPU). ProASIC3 nano devices are reprogrammable and offer time-to-market benefits at an

ASIC-level unit cost. These features enable designers to create high-density systems using existing

ASIC or FPGA design flows and tools.

ProASIC3 nano devices offer 1 kbit of on-chip, reprogrammable, nonvolatile FlashROM storage as

well as clock conditioning circuitry based on an integrated phase-locked loop (PLL). A3PN030 and

smaller devices do not have PLL or RAM support. ProASIC3 nano devices have up to 250,000 system

gates, supported with up to 36 kbits of true dual-port SRAM and up to 71 user I/Os.

ProASIC3 nano devices increase the breadth of the ProASIC3 product line by adding new features

and packages for greater customer value in high volume consumer, portable, and battery-backed

markets. Added features include smaller footprint packages designed with two-layer PCBs in mind,

low power, hot-swap capability, and Schmitt trigger for greater flexibility in low-cost and power-

sensitive applications.

Flash Advantages

Reduced Cost of Ownership

Advantages to the designer extend beyond low unit cost, performance, and ease of use. Unlike

SRAM-based FPGAs, flash-based ProASIC3 nano devices allow all functionality to be live at power-

up; no external boot PROM is required. On-board security mechanisms prevent access to all the

programming information and enable secure remote updates of the FPGA logic. Designers can

perform secure remote in-system reprogramming to support future design iterations and field

upgrades with confidence that valuable intellectual property (IP) cannot be compromised or

copied. Secure ISP can be performed using the industry-standard AES algorithm. The ProASIC3

nano device architecture mitigates the need for ASIC migration at higher user volumes. This makes

the ProASIC3 nano device a cost-effective ASIC replacement solution, especially for applications in

the consumer, networking/communications, computing, and avionics markets.

With a variety of devices under $1, Actel ProASIC3 nano FPGAs enable cost-effective

implementation of programmable logic and quick time to market.

Security

Nonvolatile, flash-based ProASIC3 nano devices do not require a boot PROM, so there is no

vulnerable external bitstream that can be easily copied. ProASIC3 nano devices incorporate

FlashLock, which provides a unique combination of reprogrammability and design security without

external overhead, advantages that only an FPGA with nonvolatile flash programming can offer.

ProASIC3 nano devices utilize a 128-bit flash-based lock and a separate AES key to secure

programmed intellectual property and configuration data. In addition, all FlashROM data in

ProASIC3 nano devices can be encrypted prior to loading, using the industry-leading AES-128

(FIPS192) bit block cipher encryption standard. The AES standard was adopted by the National

Institute of Standards and Technology (NIST) in 2000 and replaces the 1977 DES standard. ProASIC3

nano devices have a built-in AES decryption engine and a flash-based AES key that make them the

most comprehensive programmable logic device security solution available today. ProASIC3 nano

devices with AES-based security allow for secure, remote field updates over public networks such as

the Internet, and ensure that valuable IP remains out of the hands of system overbuilders, system

cloners, and IP thieves. The contents of a programmed ProASIC3 nano device cannot be read back,

although secure design verification is possible.

A dv a n c e v 0. 4

1-1

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