DATASHEET
ISL7457SRH
Radiation Hardened, SEE Hardened, Non-Inverting, Quad CMOS Driver
FN6874
Rev.3.00
Jul 28, 2017
The
ISL7457SRH
is a radiation hardened, SEE hardened,
high speed, non-inverting, quad CMOS driver. It is
capable of running at clock rates up to 40MHz and
features 2A typical peak drive capability and a nominal
ON-resistance of just 3.5Ω. The ISL7457SRH is ideal for
driving highly capacitive loads, such as storage and
vertical clocks in CCD applications. It is also well suited
to level-shifting and clock-driving applications.
Each output of the ISL7457SRH can be switched to
either the high (V
H
) or low (V
L
) supply pins, depending
on the related input pin. The inputs are compatible with
both 3.3V and 5V CMOS logic. The Output Enable (OE)
pin can be used to put the outputs into a high-impedance
state. This is especially useful in CCD applications that
disable the driver during power-down.
The ISL7457SRH also features very fast rise and fall
times, which are typically matched to within 1ns. The
propagation delay is also matched between rising and
falling edges to typically within 1.5ns.
The ISL7457SRH is available in a 16 Ld ceramic
flatpack package and specified for operation across the
full -55°C to +125°C ambient temperature range.
Features
• Electrically screened to SMD
5962-08230
• QML qualified per MIL-PRF-38535 requirements
• Full mil-temp range operation: T
A
= -55
°
C to +125
°
C
• Radiation hardness
• TID [50-300 rad(Si)/s]: 10krad(Si) minimum
• SEE hardness
• LET (SEL and SEB Immunity): 40MeV/mg/cm
2
minimum
• LET [SET =
V
OUT
< 15V,
t
< 500ns]:
40MeV/mg/cm
2
• 4 channels
• Clocking speeds up to 40MHz
• 11ns/12ns typical t
R
/t
F
with 1nF Load (15V bias)
• 1ns typical rise and fall time match (15V bias)
• 1.5ns typical prop delay match (15V bias)
• Low quiescent current - < 1mA Typical
• Fast output enable function - 12ns typical (15V bias)
• Wide output voltage range
• 0V ≤ V
L
≤ 8V
• 2.5V ≤ V
H
≤ 16.5V
• 2A typical peak drive current (15V Bias)
• 3.5Ω typical ON-resistance (15V bias)
• Input level shifters
• 3.3V/5V CMOS compatible inputs
OE
V
H
Related Literature
• For a full list of related documents, visit our website
•
ISL7457SRH
product page
Applications
• CCD drivers, clock/line drivers, level-shifters
V
S+
INx
GND
LEVEL
SHIFTER
3-STATE
CONTROL
OUTx
V
S-
V
L
Figure 1. Block Diagram
FN6874 Rev.3.00
Jul 28, 2017
Page 1 of 16
ISL7457SRH
1. Overview
1.
1.1
Overview
Ordering Information
Part Number
(Note 2)
ISL7457SRHQF
ISL7457SRHVF
ISL7457SRHVX
ISL7457SRHF/PROTO
(Note 3)
ISL7457SRHX/SAMPLE
(Note 3)
Temp. Range
(°C)
-55 to +125
-55 to +125
-55 to +125
-55 to +125
-55 to +125
Package
(RoHS Compliant)
16 Ld Flatpack
16 Ld Flatpack
Die
16 Ld Flatpack
Die
K16.A
Pkg.
Dwg. #
K16.A
K16.A
Ordering SMD
Number
(Note 1)
5962D0823001QXC
5962D0823001VXC
5962D0823001V9A
NA
NA
Notes:
1. Specifications for Rad Hard QML devices are controlled by the Defense Logistics Agency Land and Maritime (DLA). The SMD
numbers listed must be used when ordering.
2. These Intersil Pb-free Hermetic packaged products employ 100% Au plate - e4 termination finish, which is RoHS compliant and
compatible with both SnPb and Pb-free soldering operations.
3. The /PROTO and /SAMPLE are not rated or certified for Total Ionizing Dose (TID) or Single Event Effect (SEE) immunity. These
parts are intended for engineering evaluation purposes only. The /PROTO parts meet the electrical limits and conditions across
the temperature range specified in the DLA SMD and are in the same form and fit as the qualified device. The /SAMPLE die is
capable of meeting the electrical limits and conditions specified in the DLA SMD at +25°C only. The /SAMPLE is a die and does
not receive 100% screening across the temperature range to the DLA SMD electrical limits. These part types do not come with
a certificate of conformance because there is no radiation assurance testing and they are not DLA qualified devices.
1.2
Pin Configuration
ISL7457SRH
(16 Ld Flatpack)
Top View
INA
OE
INB
V
L
GND
NC
INC
IND
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
S
+
OUTA
OUTB
NC
V
H
OUTC
OUTD
V
S
-
FN6874 Rev.3.00
Jul 28, 2017
Page 2 of 16
ISL7457SRH
2. Specifications
2.
2.1
Specifications
Absolute Maximum Ratings
Parameter
Minimum
Maximum
18
-Vs - 0.3
+Vs +0.3
10
100
Unit
V
V
mA
mA
Supply Voltage (+Vs to -Vs)
Input Voltage
Input Current
Continuous Output Current per Output
Power Dissipation (P
D
T
A
= +25°C (Derate linearly at 10.1mW/°C above T
A
= +25°C)
T
A
= +125°C (Derate linearly at 10.1mW/°C above T
A
= +125°C)
T
C
= +25°C (Derate linearly at 66.7mW/°C above T
C
= +25°C)
T
C
= +125°C (Derate linearly at 66.7mW/°C above T
C
= +125°C)
ESD Rating
Human Body Model
Charged Device Model
Value
1
1.5
1.26
0.25
8.33
1.66
W
W
W
W
Unit
kV
kV
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may
adversely impact product reliability and result in failures not covered by warranty.
2.2
Thermal Information
Thermal Resistance (Typical)
JA
(°C/W)
99
JC
(°C/W)
15
16 Ld Flatpack (Notes
4, 5)
Notes:
4.
JA
is measured in free air with the component mounted on a high-effective thermal conductivity test board. See
TB379.
5. For
JC
, the “case temp” location is the center of the package underside.
Parameter
Maximum Junction Temperature
Maximum Storage Temperature Range
-65
Minimum
Maximum
+150
+150
Unit
°C
°C
2.3
Recommended Operation Conditions
Parameter
Minimum
4.5
-55
Maximum
16.5
+125
Unit
V
°C
Supply Voltage (+Vs to -Vs)
Ambient Operating Temperature Range
FN6874 Rev.3.00
Jul 28, 2017
Page 4 of 16
ISL7457SRH
2. Specifications
2.4
Electrical Specifications
Description
Test Conditions
Min
Typ
Max
Units
Typical values reflect V
S
+ = V
H
= 5V, V
S
- = V
L
= 0V, OE = V
S
+, T
A
= +25°C, unless otherwise specified.
Parameter
Input
V
IH
I
IH
V
IL
I
IL
C
IN
R
IN
Output
R
OH
R
OL
I
LEAK+
I
LEAK-
Power Supply
I
S+
I
S-
I
H
I
L
V
S
+ Supply Current
V
S
- Supply Current
V
H
Supply Current
V
L
Supply Current
INx = 0V and V
S
+
INx = 0V and V
S
+
INx = 0V and V
S
+
INx = 0V and V
S
+
0.2
-0.2
0.1
0.1
mA
mA
µA
µA
ON-Resistance V
H
to OUTx
ON-Resistance V
L
to OUTx
Positive Output Leakage Current
Negative Output Leakage Current
INx = V
S
+, I
OUTx
= -100mA
INx = 0V, I
OUTx
= +100mA
INx = V
S
+, OE = 0V, OUTx = V
S
+
INx = V
S
+, OE = 0V, OUTx = V
S
-
8
6
5
-5
Ω
Ω
nA
nA
Logic “1” Input Voltage
Logic “1” Input Current
Logic “0” Input Voltage
Logic “0” Input Current
Input Capacitance
Input Resistance
INx = 0V
INx = V
S
+
1.3
10
1.23
-5
5.7
500
V
nA
V
nA
pF
MΩ
Switching Characteristics
t
R
t
F
t
RF
t
D
+
t
D
-
t
DD
t
ENABLE
t
DISABLE
Rise Time
Fall Time
t
R
, t
F
Mismatch
Turn-On Delay Time
Turn-Off Delay Time
t
D
+, t
D
- Mismatch
Enable Delay Time
Disable Delay Time
INx = 0V to 4.5V step, C
L
= 1nF
INx = 4.5V to 0V step, C
L
= 1nF
C
L
= 1nF
INx = 0V to 4.5V step, C
L
= 1nF
INx = 4.5V to 0V step, C
L
= 1nF
C
L
= 1nF
INx = V
S
+, OE = 0V to 4.5V step, R
L
= 1kΩ
INx = V
S
+, OE = 4.5V to 0V step, R
L
= 1kΩ
23
20
3
20
22
2
21
46
ns
ns
ns
ns
ns
ns
ns
ns
FN6874 Rev.3.00
Jul 28, 2017
Page 5 of 16
Talking
京公网安备 11010802033920号
EEWORLD
