SaRonix
Crystal Clock Oscillator
Technical Data
Frequency Range:
Frequency Stability:
32 MHz to 125 MHz
±20, ±25, ±50 or ±100 ppm over all conditions: calibration
tolerance, operating temperature, input voltage change, load
change, aging*, shock and vibration.
*1 year @ +40°C average ambient operating temperature
0 to +70°C or -40 to +85°C
-55 to +125°C
3.3 & 5V, ACMOS, LVCMOS
ST41xx Series
Temperature Range:
Operating:
Storage:
Supply Voltage:
Recommended Operating:
Supply Current:
ACTUAL SIZE
+5V ±5% or 3.3V ±10%
50mA typ, 65mA, 35mA max @ 3.3V
Output Drive:
Symmetry:
0 to +70°C:
-40 to +85°C:
Rise & Fall Times:
Logic 0:
Logic 1:
Load:
Period Jitter RMS:
ACMOS
TTL
TTL
60+ to 125 MHz 32 to 60 MHz 60+ to 125 MHz
45/55%
45/55%
45/55%
40/60%
45/55%
40/60%
(45/55% @ 3.3V)
2ns max 20% to 80% V
DD
1.5ns max 0.5 to 2.5V
10% V
DD
max or 20% V
DD
max @ 3.3V
80% V
DD
min or 80% V
DD
min @ 3.3V
50Ω ACMOS or 95Ω ACMOS @ 3.3V
13ps max 32 to 72 MHz
20ps max 72+ to 125 MHz, 0 to +70°C
25ps max 72+ to 125 MHz, -40 to +85°C
ACMOS
32 to 60 MHz
45/55%
45/55%
Description
A crystal controlled, low-current oscilla-
tor providing precise rise and fall times
to drive ACMOS/LVCMOS loads. The
tri-state function enables the output to go
high impedance. Available in either a 14
or an 8 pin DIP compatible, resistance
welded, all metal case. Pin 7 ( or Pin 4 )
is grounded to case to reduce EMI. True
SMD DIL 14 version also available, uti-
lizing new adaptor technology (see sepa-
rate data sheet for package dimensions).
Applications & Features
•
•
•
•
•
•
•
•
Fiber Channel
Gigabit Ethernet
HCMOS/ACMOS/LVCMOS MPU's
3.3 or 5V operation
High Drive capability
Tri-State output standard
Short circuit protected output
Plastic SMD available, see ST41xH
Series data sheet.
• Ceramic SMD available, see S19xx
Series data sheet.
• True SMD version available, select
option S in part number builder (see
separate data sheet for package dimen-
sions).
Mechanical:
Shock:
Solderability:
Terminal Strength:
Vibration:
Solvent Resistance:
Resistance to Soldering Heat:
MIL-STD-883, Method 2002, Condition B
MIL-STD-883, Method 2003
MIL-STD-883, Method 2004, Condition B2
MIL-STD-883, Method 2007, Condition A
MIL-STD-202, Method 215
MIL-STD-202, Method 210, Condition A, B or C
( I or J for Gull Wing or SMD)
Environmental:
Gross Leak Test:
Fine Leak Test:
Thermal Shock:
Moisture Resistance:
Part Numbering Guide
MIL-STD-883,
MIL-STD-883,
MIL-STD-883,
MIL-STD-883,
Method
Method
Method
Method
1014, Condition C
1014, Condition A2
1011, Condition A
1004
ST41 3 0 A – 106.2500 (T)
Series
Type
3 = 3.3V LVCMOS
5 = 5V TTL
6 = 5V ACMOS
Package Style
0 = Full Size, Metal
9 = Half Size, Metal
J = Half Size, Metal, Gull Wing
K = Full Size, Metal, Gull Wing
S = True SMD Adaptor
(see product photo)
Stability Tolerance
AA = ±20 ppm, 0 to +70°C
A = ±25 ppm, 0 to +70°C
B = ±50 ppm, 0 to +70°C
C = ±100 ppm, 0 to +70°C
E = ±50 ppm, -40 to +85°C
F = ±100 ppm, -40 to +85°C
DS-183
REV C
Packing Method
(T) = Tape & Reel for SMD versions
full reel increments only (200pcs)
Blank = Bulk
Frequency
SaRonix
http://www.pericom.com/saronix
SaRonix
Crystal Clock Oscillator
Technical Data
Package Details
FULL SIZE PACKAGE
0.91
.036
max
21.0 max
.825
5.08
max
.200
.46±.076
.018±.003
15.24±.13
.600±.005
Pin 1
Tri-State
Control
Pin 7
GND
6.35±.51
.250±.020
LOGIC 1
80% V
DD
50% V
DD
20% V
DD
LOGIC 0
SYMMETRY
SYMMETRY
2.5 VDC
1.5 VDC
0.5 VDC
GND
T
r
3.3 & 5V, ACMOS, LVCMOS
ST41xx Series
Output Waveform
CMOS
T
f
T
r
TTL
T
f
V
DD
Tri-State Logic Table
Pin 1 Input
Logic 1 or NC
Logic 0 or GND
Pin 8 (5) Output
Oscillation
High Impedance
Required Input Levels on Pin 1:
Logic 1 = 2.2V min
Logic 0 = 0.8V max
13.0 max
.510
Test Circuits
Pin 14
VDC
(4) Glass
Insulators
7.75
max
.305
Pin 8
Output
mA
M
Pad 4
V
CC
POWER
SUPPLY
TEST
POINT
ACMOS
50Ω Load
Pad 3
Standard Marking Format
**
Includes Date Code, Frequency, Part Number
OUT
50Ω
SARONIX
XTAL OSC
VM
.01 µF
OSCILLATOR
GND
0.01 µF
Pad 1
Pad 2
Denotes Pin 1
HALF SIZE PACKAGE
13.0 max
.510
0.91 max
.036
5.08 max
.200
6.35±.51
.250±.020
7.62±.20
.300±.008
Pin 4
GND
TRI-STATE INPUT
(current limited on fixture)
50Ω ACMOS TEST CIRCUIT
Ω
.46±.08
.018±.003
Pin 1
Tri-State
1.5
.059
TEST
POINT
mA
M
Pad 4
V
CC
OUT
ACMOS
95Ω Load
Pad 3
95Ω
120°
13.0
.510
max
120°
120°
7.62±.20
.300±.008
POWER
SUPPLY
Pin 5
Output
.01 µF
OSCILLATOR
GND
0.01 µF
VM
Pad 1
Pad 2
Pin 8
V
DD
Glass
Insulators
Standard Marking Format
**
Includes Date Code, Frequency, Part Number
TRI-STATE INPUT
(current limited on fixture)
95Ω ACMOS TEST CIRCUIT
Ω
SARONIX
Denotes Pin 1
**
Exact location of items may vary
Scale: None (Dimensions in
mm
)
inches
All specifications are subject to change without notice.
DS-183
REV C
SaRonix
http://www.pericom.com/saronix
FPGA/CPLD
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