LD49150XX08
LD49150XX10, LD49150XX12
1.5 A very low drop for low output voltage regulator
Features
■
Input voltage range:
– V
I
= 1.4 V to 5.5 V
– V
BIAS
= 3 V to 6 V
Stable with ceramic capacitor
±1.5 % initial tolerance
Maximum dropout voltage (V
I
- V
O
) of 200 mV
over temperature
Adjustable output voltage down to 0.8 V
Ultra fast transient response (up to 10 MHz
bandwidth)
Excellent line and load regulation
specifications
Logic controlled shutdown option
Thermal shutdown and current limit protection
Junction temperature range: - 25 °C to 125 °C
PPAK
DFN6 (3x3 mm)
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Description
The LD49150xx is a high-bandwidth, low-dropout,
1.5 A voltage regulator, ideal for powering core
voltages of low-power microprocessors. The
LD49150xx implements a dual supply
configuration allowing for very low output
impedance and very fast transient response. The
LD49150xx requires a bias input supply and a
main input supply, allowing for ultra-low input
voltages on the main supply rail. The input supply
operates from 1.4 V to 5.5 V and the bias supply
requires between 3 V and 6 V for proper
operation. The LD49150xx offers fixed output
voltages from 0.8 V to 1.8 V and adjustable output
voltages down to 0.8 V. The LD49150xx requires a
minimum output capacitance for stability, and
work optimally with small ceramic capacitors.
Applications
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Graphics processors
PC add-in cards
Microprocessor core voltage supply
Low voltage digital ICs
High efficiency linear power supplies
SMPS post regulators
Table 1.
Device summary
Order codes
Output voltages
0.8 V
(2)
LD49150PU10R
LD49150PU12R
1.0 V
1.2 V
PPAK (tape and reel)
LD49150PT08R
LD49150PT10R
LD49150PT12R
1. Available on request.
2. Adjustable version.
DFN6 (tape and reel)
(1)
June 2010
Doc ID 13446 Rev 3
1/22
www.st.com
22
Contents
LD49150XX08, LD49150XX10, LD49150XX12
Contents
1
2
3
4
5
6
7
8
Typical application circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Alternative application circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Typical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Application hints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
8.1
8.2
8.3
8.4
8.5
8.6
8.7
8.8
8.9
8.10
Input supply voltage (V
IN
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Bias supply voltage (V
BIAS
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
External capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Output capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Minimum load current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Power sequencing recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Power dissipation/heatsinking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Heatsinking PPAK package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Adjustable regulator design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
9
10
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
2/22
Doc ID 13446 Rev 3
LD49150XX08, LD49150XX10, LD49150XX12
Typical application circuits
1
Figure 1.
Typical application circuits
Adjustable version
Figure 2.
Fixed version with Enable
Doc ID 13446 Rev 3
3/22
Alternative application circuits
LD49150XX08, LD49150XX10, LD49150XX12
2
Figure 3.
Alternative application circuits
Single supply voltage solution
Figure 4.
LD49150xx plus DC-DC pre-regulator to reduce power dissipation
4/22
Doc ID 13446 Rev 3
LD49150XX08, LD49150XX10, LD49150XX12
Pin configuration
3
Figure 5.
Pin configuration
Pin connections (top view for PPAK, bottom view for DFN)
DFN6 (3 x 3 mm)
PPAK
Table 2.
Pin n° for
PPAK
Pin description
Pin n° for
DFN
Symbol
EN
Note
For fixed versions: Enable (Input) - Logic High = Enable, Logic Low =
Shutdown.
For adjustable versions: Adjustable regulator feedback input. Connect to
resistor voltage divider.
Input voltage which supplies current to the output power device.
Ground (TAB is connected to ground).
Regulator output.
Input bias voltage for powering all circuitry on the regulator with the
exception of the output power device.
Not connect.
1
2
ADJ
2
3
4
5
3
1
4
6
5
V
IN
GND
V
OUT
V
BIAS
N.C.
Doc ID 13446 Rev 3
5/22
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