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3771G-18

Description
PLL Based Clock Driver, 3771 Series, 4 True Output(s), 0 Inverted Output(s), PDSO16, 0.40 MM, 0.65 MM PITCH, MO-153, TSSOP-28
Categorylogic    logic   
File Size175KB,8 Pages
ManufacturerIDT (Integrated Device Technology)
Download Datasheet Parametric Compare View All

3771G-18 Overview

PLL Based Clock Driver, 3771 Series, 4 True Output(s), 0 Inverted Output(s), PDSO16, 0.40 MM, 0.65 MM PITCH, MO-153, TSSOP-28

3771G-18 Parametric

Parameter NameAttribute value
Is it lead-free?Contains lead
Is it Rohs certified?incompatible
MakerIDT (Integrated Device Technology)
Parts packaging codeTSSOP
package instruction0.40 MM, 0.65 MM PITCH, MO-153, TSSOP-28
Contacts16
Reach Compliance Codenot_compliant
series3771
Input adjustmentSTANDARD
JESD-30 codeR-PDSO-G16
JESD-609 codee0
length5 mm
Logic integrated circuit typePLL BASED CLOCK DRIVER
Humidity sensitivity level1
Number of functions1
Number of inverted outputs
Number of terminals16
Actual output times4
Maximum operating temperature70 °C
Minimum operating temperature
Package body materialPLASTIC/EPOXY
encapsulated codeTSSOP
Encapsulate equivalent codeTSSOP16,.25
Package shapeRECTANGULAR
Package formSMALL OUTLINE, THIN PROFILE, SHRINK PITCH
Peak Reflow Temperature (Celsius)225
power supply3.3 V
Certification statusNot Qualified
Maximum seat height1.2 mm
Maximum supply voltage (Vsup)3.465 V
Minimum supply voltage (Vsup)3.135 V
Nominal supply voltage (Vsup)3.3 V
surface mountYES
Temperature levelCOMMERCIAL
Terminal surfaceTin/Lead (Sn85Pb15)
Terminal formGULL WING
Terminal pitch0.65 mm
Terminal locationDUAL
Maximum time at peak reflow temperature30
width4.4 mm
DATASHEET
DTV, STB CLOCK SOURCE
Description
The ICS3771-18 provides clock generation and
conversion for clock rates commonly needed in HDTV
digital video equipment. The ICS3771-18 uses the
latest PLL technology to provide excellent phase noise
and long term jitter performance for superior
synchronization and S/N ratio.
For audio sampling clocks generated from 27 MHz, use
the ICS661.
Please contact IDT if you have a requirement for an
input and output frequency not included in this
document. IDT can rapidly modify this product to meet
special requirements.
ICS3771-18
Features
Integrated Phase-Lock Loop
Low jitter, high accuracy outputs
3.3 V operation
Packaged in 16-pin TSSOP
RoHS 6 (green and lead free) compliant packaging
Exact (0 ppm) multiplication ratios
Pin compatible to CY24204-3
Block Diagram
VDD
VDDL
AVDD
27 MHz
CLKIN
PLL Clock
Synthesis
Output
Multiplexer
and Dividers
CLK1
CLK2
REFOUT1
REFOUT2
FS1:0
2
2
GND
GNDA
OE
IDT™ / ICS™
DTV, STB CLOCK SOURCE
1
ICS3771-18
REV B 111307

3771G-18 Related Products

3771G-18
Description PLL Based Clock Driver, 3771 Series, 4 True Output(s), 0 Inverted Output(s), PDSO16, 0.40 MM, 0.65 MM PITCH, MO-153, TSSOP-28
Is it lead-free? Contains lead
Is it Rohs certified? incompatible
Maker IDT (Integrated Device Technology)
Parts packaging code TSSOP
package instruction 0.40 MM, 0.65 MM PITCH, MO-153, TSSOP-28
Contacts 16
Reach Compliance Code not_compliant
series 3771
Input adjustment STANDARD
JESD-30 code R-PDSO-G16
JESD-609 code e0
length 5 mm
Logic integrated circuit type PLL BASED CLOCK DRIVER
Humidity sensitivity level 1
Number of functions 1
Number of terminals 16
Actual output times 4
Maximum operating temperature 70 °C
Package body material PLASTIC/EPOXY
encapsulated code TSSOP
Encapsulate equivalent code TSSOP16,.25
Package shape RECTANGULAR
Package form SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
Peak Reflow Temperature (Celsius) 225
power supply 3.3 V
Certification status Not Qualified
Maximum seat height 1.2 mm
Maximum supply voltage (Vsup) 3.465 V
Minimum supply voltage (Vsup) 3.135 V
Nominal supply voltage (Vsup) 3.3 V
surface mount YES
Temperature level COMMERCIAL
Terminal surface Tin/Lead (Sn85Pb15)
Terminal form GULL WING
Terminal pitch 0.65 mm
Terminal location DUAL
Maximum time at peak reflow temperature 30
width 4.4 mm
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