5962R9475403QLX datasheet, PDF

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5962R9475403QLX: DescriptionOT PLD, 20ns, CMOS, 1.200 X 0.300 INCH, 2.54 MM PITCH, CERAMIC, DIP-24; CategoryProgrammable logic devices Programmable logic; File Size1MB，17 Pages; ManufacturerDefense Logistics Agency

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5962R9475403QLX Overview

OT PLD, 20ns, CMOS, 1.200 X 0.300 INCH, 2.54 MM PITCH, CERAMIC, DIP-24

5962R9475403QLX Parametric

Parameter Name	Attribute value
Maker	Defense Logistics Agency
package instruction	DIP,
Reach Compliance Code	unknown
ECCN code	3A001.A.2.C
Other features	10 MACROCELLS
maximum clock frequency	32 MHz
length	30.48 mm
Dedicated input times	11
Number of I/O lines	10
Maximum operating temperature	125 °C
Minimum operating temperature	-55 °C
organize	11 DEDICATED INPUTS, 10 I/O
Output function	MACROCELL
Package body material	CERAMIC, METAL-SEALED COFIRED
encapsulated code	DIP
Package form	IN-LINE
Programmable logic type	OT PLD
propagation delay	20 ns
Certification status	Not Qualified
Filter level	MIL-PRF-38535 Class Q
Maximum seat height	4.2164 mm
Maximum supply voltage	5.5 V
Minimum supply voltage	4.5 V
Nominal supply voltage	5 V
surface mount	NO
technology	CMOS
Temperature level	MILITARY
Terminal form	THROUGH-HOLE
Terminal pitch	2.54 mm
Terminal location	DUAL
total dose	100k Rad(Si) V
width	7.62 mm

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Standard Products

UT22VP10 Universal RAD

PAL

Data Sheet

Feb. 1999

FEATURES

High speed Universal RAD

PAL

- tPD: 15.5ns, 20ns, 25ns maximum

fMAX1: 33MHz maximum external frequency

Supported by industry-standard programmer

Amorphous silicon anti-fuse

Radiation-hardened process and design; total dose irradia-

tion testing to MIL-STD-883, Method 1019

- Total dose: 1.0E6 rads(Si)

- Upset threshold 50 MeV-cm

/mg (min)

- Latchup immune(LET>109 MeV-cm

/mg)

QML Q & V compliant

Packaging options:

- 24-pin 100-mil center DIP (0.300 x 1.2)

- 24-lead flatpack (.45 x .64)

- 28-lead quad-flatpack (.45 x .45)

Standard Military Drawing 5962-94754 available

Variable product terms, 8 to 16 per output

10 user-programmable output macrocells

- Registered or combinatorial operation

- Output driver polarity control selectable

- Two feedback paths available

Asynchronous and synchronous RAD

PAL

operation

- Synchronous PRESET

- Asynchronous RESET

Up to 22 input and 10 output drivers may be configured

- CMOS & TTL-compatible input and output levels

- Three-state output drivers

Reset

PROGRAMMABLE ARRAY LOGIC

(132 X 44)

Preset

Macrocell

Figure 1. Block Diagram

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