Standard Products
UT200SpW4RTR 4-Port SpaceWire Router
Datasheet
April 8, 2013
www.aeroflex.com/SpaceWire
FEATURES
4-Port SpaceWire Router with a system interface port for a
total of 5 ports
Data rates up to 200Mbps full duplex on all 4 SpaceWire
ports
Compliant to the SpaceWire Standard, Document Number
ECSS-E-ST-50-12C (http://www.ecss.nl/)
Group adaptive routing for 2 ports when using logical
addressing
Replicated lookup tables for each receive port no arbitration
is necessary when accessing lookup table data
Host (FIFO) clock max frequency: 50MHz for 200Mbps
-9 by 128 receive and transmit FIFOs on each port
Non-blocking cross-point switch connecting any receive
port to any transmit port
Path and logical addressing support
Internal status/error registers accessible via the
configuration protocol
Routing is table accessible via the configuration protocol
which holds the logical address to transmit port mapping
Any SpaceWire port can READ or WRITE to the
configuration port, along with the host processor, by
utilizing the configuration protocol
Internal control logic to support the operation of arbitration
and group adaptive routing. (Group Adaptive routing for 2
ports)
In external time-code interface comprising TICK_IN,
TICK_OUT and current tick count value
System Interface Features
- Low-power FIFO memories
- Clocked PUSH and POP interfaces
- Hard set Full/Almost Full/Empty/Almost Empty flags
- SpaceWire In/out ports are controlled by separate clock
and enable signals. Transmit FIFO input port is controlled
by a free-running clock (HOST_CLK).
Cold spare on LVDS pins
3.3V I/O Supply (V
DD
)
2.5V Core Supply (V
DDC
)
ESD rating Class 2 2000 V for LVDS pins
Temperature range: -40°C to +105°C
Operational environment:
- Total-dose: 100 krad(Si)
- Latchup immune (LET >100 MeV-cm
2
/mg)
Packaging options:
- 255-lead CLGA
- 255-lead CBGA
- 255-lead CCGA
Standard Microcircuit Drawing 5962-08244
-QML Q and QML V
INTRODUCTION
The Aeroflex UT200SpW4RTR is a 4-Port Router capable of
operating at data rates from 10 to 200 Mbps. A parallel host
interface is also provided for a total of 5 ports on the router. The
router implements a non-blocking crosspoint switch and a
"Round Robin" arbitration scheme allowing all 5 receive ports
access to all 5 transmit ports.
Path and logical addressing are supported (Per ECSS-E-ST-50-
12C) and lookup table storage is replicated 5 times giving each
receive port a dedicated block of memory for logical addressing.
Configuration of lookup tables, as well as access to internal
registers may occur through any of the 5 ports using a simple
configuration protocol. A group adaptive function is also
provided for 2 ports when implementing logical addressing.
Each of the four SpaceWire ports is capable of running at an
independent speed. This allows for systems to be configured
with nodes/instruments running at different speeds. If one
node/instrument does not need to be sampled as often as another
a more efficient power management scheme can be achieved.
The physical interfaces can be either a LVDS or LVCMOS
interface. This allows the user to select the interface that best
meets system and reliability requirements. The LVDS interface
can directly connect and drive up to 10 meters of cable. The
LVCMOS interface must interface to LVDS drivers and
receivers.
Independent look up table memory space is provided for each
port. Having separate look up tables reduces bottle necks by
allowing each port access to a non shared lookup table.
1
Aeroflex UT200SpW4RTR
4 Port SpaceWire Router
Port 1
TX1_D_LV
2
TX1_S_LV
2
LVDS
Configuration
Aeroflex SpaceWire
LPH Core
Tx_int
TX_FIFO
RX1_D_LV
2
wr_Logic_1
arbiter
RX_FIFO
Rx_int
RX1_S_LV
2
TX1_D
TX1_S
Phy
Interface
Init
Look Up Table
Write
8
Port_addr_1
look_up_1
Ram Block
RX1_D
LVCMOS
rd_Logic_1
Port_addr_2
Port_addr_3
Port 2
Port_addr_4
look_up_ext
we
din
we
din
RX1_S
TXCLK_IN_1
TXCLK_IN_2
TXCLK_IN_3
TXCLK_IN_4
TX_DIV
5
TX2_D_LV
2
TX2_S_LV
2
LVDS
wr_Logic_2
arbiter
Port_addr_ext
RX_FIFO
Rx_int
Aeroflex SpaceWire
LPH Core
Tx_int
TX_FIFO
Ram Block
RX2_D_LV
2
Phy
Interface
Init
RX2_S_LV
2
TX2_D
TX2_S
LVCMOS
Port 3
TX_DATA
System
Transmit
FIFO
9
RX2_D
rd_Logic_2
rd_Logic_ext
Figure 1. UT200SpW4RTR SpaceWire 4-Port Router Block Diagram
2
LVDS
arbiter
Init
RX_FIFO
Rx_int
RX2_S
TX_PUSH
TX_FULL
TX_AFULL
Write
Capable
HOST_CLK
RX_DATA
9
RX_POP
wr_Logic_ext
arbiter
TX3_D_LV
2
TX3_S_LV
2
wr_Logic_3
Aeroflex SpaceWire
LPH Core
Tx_int
TX_FIFO
RX3_D_LV
2
Phy
Interface
LVCMOS
Port 4
2
System
Receive
FIFO
Read
Capable
RX3_S_LV
TX3_D
TX3_S
rd_Logic_3
RX_EMPTY
RX_AEMPTY
RX3_D
RX3_S
TIME_CODE
8
wr_Logic_4
arbiter
TX4_D_LV
2
TX4_S_LV
2
LVDS
Init
RC_FIFO
Rc_int
Aeroflex SpaceWire
LPH Core
Tx_int
TX_FIFO
RX4_D_LV
2
Phy
Interface
LVCMOS
Time Code
Manager
TICK_IN
TICK_OUT
RX4_S_LV
2
TX4_D
TX4_S
rd_Logic_4
RX4_D
RX4_S
APPLICATIONS INFORMATION
Aeroflex Colorado Springs' UT200SpW4RTR 4-Port Router
offers a highly adaptable solution for a distributed network. The
number of ports allows for a very reliable system where multi-
ple nodes can be connected together to gain performance. Using
the non-blocking cross-point switch the shortest path between
nodes can be configured. Each node can transmit and receive
packets and each connection between nodes can carry multiple
packets. The 4-Port Router is full duplex on each of the ports.
The router also allows for a small Centralized network config-
uration.
1.0 INTERFACES
1.1 SpaceWire
The UT200SpW4RTR 4-Port Router provides four
ECSS-E-ST-50-12C compliant node interfaces. Each node con-
tains a transmit and receive FIFO used to buffer data being sent
within the network. The transmit FIFO takes data from a host
system and transmits it to a node. Where as the receive FIFO
accepts data from a node and passes it to the host system. A host
system is what the node is connected to and can be a micropro-
cessor, computer, sensor or memory unit and is responsible for
data management.
1.1.1 Port Initialization
All four ports follow the initialization procedure as defined
in ECSS-E-ST-50-12C. Following are the key components of
the initialization process. After a reset or disconnect the link
will initiate operation at a signaling rate of 10 Mbps, ±1 Mbps.
This provides the system with a common data rate while the
system is checked for proper operation. Once the operation of
the system is validated each of the four ports will switch to the
specified transmit data rate. Each of the four ports must be ca-
pable of running at 10 ± 1 Mbps.
1.2 System Interface
The UT200SpW4RTR 4-Port Router provides a system
interface to the user in the form of Receive and Transmit
FIFO's. Each FIFO is 9 bits wide by 128 deep. Data format for
the FIFO is 8-bits of data [7:0] and one bit [8] to indicate when
an EOP or an EEP has been received. A EOP is an End-of-
Packet marker and is used to indicate that a packet of data has
been successfully sent. An EEP is an Error-End-of-Packet and
signals that there was an error with in the packet. Table 1 shows
the EOP/EEP handling.
System
Transmit
FIFO
Write
Capable
TX_DATA
TX_PUSH
TX_FULL
TX_AFULL
9
HOST_CLK
Figure 2. System Transmit Interface
1.2.1 System Port Transmit FIFO
The Transmit FIFO is write capable by the user and is 9 bits
wide by 128 deep. Full (TX_FULL) and Almost Full
(TX_AFULL) flags are provided to help the user prevent over-
writing the FIFO. Data will be written into the FIFO on the ris-
ing edge of the clock when TX_PUSH is “Low”. The levels of
the Almost Full flags can not be changed by the user.
RX_DATA
9
RX_POP
RX_EMPTY
RX_AEMPTY
HOST_CLK
System
Receive
FIFO
Read
Capable
Figure 3. System Receive Interface
1.2.2 System Port Receive FIFO
A second 9 bit wide by 128 deep FIFO is provided for the user
interface to receive data. Data received from one of the
SpaceWire ports is read from the receive FIFO on the rising
edge of the HOST clock when RX_POP is “Low”. This FIFO
is first Byte Fall Through.
1.3 SpaceWire Physical Interface
The UT200SpW4RTR provides two different physical interfac-
es to the user. The first is on chip LVDS that can drive cable
lengths up to 10 meters. The second is single ended LVCMOS
in the event the user wishes to use discrete LVDS drivers and
receivers. Examples of these two configurations are shown in
Figures 4 and 5. In Figure 5 the external LVDS devices are
Aeroflex quad drivers and receivers.
Table 1. EOP and EEP Handling
9-bit Data
100000000
100000001
Character Type
EOP
EEP
3
SpaceWire Bus
TX1_D_LV
TX1_S_LV
RX1_D_LV
RX1_S_LV
TX1_D
TX1_S
RX1_D
RX1_S
TX2_D_LV
TX2_S_LV
RX2_D_LV
RX2_S_LV
TX2_D
TX2_S
RX2_D
RX2_S
TX3_D_LV
TX3_S_LV
RX3_D_LV
RX3_S_LV
TX3_D
TX3_S
RX3_D
RX3_S
TX4_D_LV
TX4_S_LV
RX4_D_LV
RX4_S_LV
TX4_D
TX4_S
RX4_D
RX4_S
2
2
2
2
LVDS
Port 1
LVCMOS
UT200SpW4RTR
4 Port SpaceWire
Router
SpaceWire Bus
2
2
2
2
LVDS
Port 2
LVCMOS
SpaceWire Bus
2
2
2
2
LVDS
Port 3
LVCMOS
SpaceWire Bus
2
2
2
2
LVDS
Port 4
LVCMOS
Figure 4. 4-Port Router On Chip LVDS Interface
4
TX1_D_LV
TX1_S_LV
RX1_D_LV
RX1_S_LV
TX1_D
TX1_S
RX1_D
RX1_S
TX2_D_LV
TX2_S_LV
RX2_D_LV
RX2_S_LV
TX2_D
TX2_S
RX2_D
RX2_S
TX3_D_LV
TX3_S_LV
RX3_D_LV
RX3_S_LV
TX3_D
TX3_S
RX3_D
RX3_S
TX4_D_LV
TX4_S_LV
RX4_D_LV
RX4_S_LV
TX4_D
TX4_S
RX4_D
RX4_S
2
2
2
2
LVDS
Port 1
LVCMOS
UT200SpW4RTR
4 Port SpaceWire
Router
UT54LVDS031LV
SpaceWire Bus
UT54LVDS032LV
2
2
2
2
LVDS
Port 2
LVCMOS
UT54LVDS031LV
SpaceWire Bus
UT54LVDS032LV
2
2
2
2
LVDS
Port 3
LVCMOS
UT54LVDS031LV
SpaceWire Bus
UT54LVDS032LV
2
2
2
2
LVDS
Port 4
LVCMOS
UT54LVDS031LV
SpaceWire Bus
UT54LVDS032LV
Figure 5. 4-Port Router External LVDS Interface
5
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