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5962R0626302VXX

Description
Support Circuit, CDFP28, CERAMIC, DFP-28
CategoryWireless rf/communication    Telecom circuit   
File Size158KB,15 Pages
ManufacturerCobham Semiconductor Solutions
Download Datasheet Parametric View All

5962R0626302VXX Overview

Support Circuit, CDFP28, CERAMIC, DFP-28

5962R0626302VXX Parametric

Parameter NameAttribute value
MakerCobham Semiconductor Solutions
Parts packaging codeDFP
package instructionDFP,
Contacts28
Reach Compliance Codeunknown
JESD-30 codeS-CDFP-F28
JESD-609 codee0/e4
length9.652 mm
Number of functions1
Number of terminals28
Maximum operating temperature125 °C
Minimum operating temperature-40 °C
Package body materialCERAMIC, METAL-SEALED COFIRED
encapsulated codeDFP
Package shapeSQUARE
Package formFLATPACK
Certification statusNot Qualified
Filter levelMIL-PRF-38535 Class V
Maximum seat height2.921 mm
Nominal supply voltage3.3 V
surface mountYES
Telecom integrated circuit typesSUPPORT CIRCUIT
Temperature levelAUTOMOTIVE
Terminal surfaceTIN LEAD/GOLD
Terminal formFLAT
Terminal pitch0.635 mm
Terminal locationDUAL
total dose100k Rad(Si) V
width9.652 mm
Standard Products
UT200SpWPHY01 SpaceWire Physical Layer Transceiver
Datasheet
August, 2006
FEATURES
2-bit Serializer/Deserializer (SerDes) functionality
LVDS physical layer
Data rates to 200 Mbits/sec
Data/Strobe transmit skew <500pS
3.3V power supply
Cold spare on LVDS pins
Radiation-hardened design; total dose irradiation testing to
MIL-STD-883 Method 1019
- Total-dose: 100 krad(Si)
- Latchup immune (LET > 110 MeV-cm
2
/mg)
ESD rating Class 1
Packaged in a 28-pin flatpack
Standard Microcircuit Drawing 5962-06232
- QML Q and V compliant part
INTRODUCTION
Aeroflex Colorado Springs’ UT200SpWPHY01 Physical Layer
Transceiver (PHY) is designed to handle the critical timing
issues associated with the SpaceWire Data/Strobe Encoding
scheme.
The receiver operates on both edges of the recovered RxClk and
provides data on the digital outputs in bit pairs. The transmitter
operation is the reverse of the receiver. Bit pairs of data and
strobe are written into the device on the WrClk signal and the
PHY serializes data and strobe onto the LVDS bus using the
TxClk signal. The advantages of this SerDes functionality is the
interfacing FPGA or ASIC can run at reduced clock rate with
high-speed clock not requiring a stringent phase relationship.
RmtLBE
TxD0
TxD1
TxS0
TxS1
WrClk
TxClk
TxOE
TxD+
Transmit
Block
TxOE
TxD-
TxS+
TxS-
RxD+
RxD-
RxS+
RxS-
RxDR
RxDF
RxClk
RST
LclLBE
Figure 1. UT200SpWPHY01 SpaceWire PHY Chip Block Diagram
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