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5692H9865204QYA

Description
QUAD LINE RECEIVER, CDSO16, CERAMIC, DFP-16
CategoryAnalog mixed-signal IC    Drivers and interfaces   
File Size111KB,13 Pages
ManufacturerCobham Semiconductor Solutions
Download Datasheet Parametric View All

5692H9865204QYA Overview

QUAD LINE RECEIVER, CDSO16, CERAMIC, DFP-16

5692H9865204QYA Parametric

Parameter NameAttribute value
MakerCobham Semiconductor Solutions
Parts packaging codeDFP
package instructionDFP,
Contacts16
Reach Compliance Codeunknown
ECCN codeEAR99
Input propertiesDIFFERENTIAL
Interface integrated circuit typeLINE RECEIVER
Interface standardsGENERAL PURPOSE
JESD-30 codeR-CDSO-F16
Number of functions4
Number of terminals16
Maximum operating temperature125 °C
Minimum operating temperature-55 °C
Package body materialCERAMIC, METAL-SEALED COFIRED
encapsulated codeDFP
Package shapeRECTANGULAR
Package formSMALL OUTLINE
Certification statusNot Qualified
Maximum receive delay1.9 ns
Number of receiver bits4
Filter levelMIL-PRF-38535 Class Q
Maximum seat height2.921 mm
Maximum supply voltage3.6 V
Minimum supply voltage3 V
Nominal supply voltage3.3 V
surface mountYES
technologyCMOS
Temperature levelMILITARY
Terminal formFLAT
Terminal pitch1.27 mm
Terminal locationDUAL
total dose1M Rad(Si) V
width6.731 mm
Standard Products
UT54LVDS032LV/E Low Voltage Quad Receiver
Data Sheet
December, 2008
www.aeroflex.com/lvds
FEATURES
>400.0 Mbps (200 MHz) switching rates
+340mV differential signaling
3.3 V power supply
TTL compatible outputs
Cold spare all pins
Ultra low power CMOS technology
1.9ns maximum propagation delay
200ps maximum differential skew
Operational environment; total dose irradiation testing to
MIL-STD-883 Method 1019
- Total-dose: 300 krad(Si) and 1Mrad(Si)
- Latchup immune (LET > 100 MeV-cm
2
/mg)
Packaging options:
- 16-lead flatpack (dual in-line)
Standard Microcircuit Drawing 5962-98652
- QML Q and V compliant part
INTRODUCTION
The UT54LVDS032LV Quad Receiver is a quad CMOS
differential line receiver designed for applications requiring
ultra low power dissipation and high data rates. The device is
designed to support data rates in excess of 400.0 Mbps (200
MHz) utilizing Low Voltage Differential Signaling (LVDS)
technology.
The UT54LVDS032LV accepts low voltage (340mV)
differential input signals and translates them to 3V CMOS
output levels. The receiver supports a three-state function that
may be used to multiplex outputs. The receiver also supports
OPEN, shorted and terminated (100
Ω)
input fail-safe. Receiver
output will be HIGH for all fail-safe conditions.
The UT54LVDS032LV and companion quad line driver
UT54LVDS031LV provides new alternatives to high power
pseudo-ECL devices for high speed point-to-point interface
applications.
All pins have Cold Spare buffers. These buffers will be high
impedance when V
DD
is tied to V
SS
.
R
IN1+
R
IN1-
+
R1
-
R
OUT1
R
IN2+
R
IN2-
+
R2
-
R
OUT2
R
IN3+
R
IN3-
+
R3
-
R
OUT3
R
IN4+
R
IN4-
EN
EN
+
R4
-
R
OUT4
Figure 1. UT54LVDS032LV Quad Receiver Block Diagram
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