530AB521M000DGR datasheet, PDF

Datasheet> All Categories > Passive components> oscillator> 530AB521M000DGR

530AB521M000DGR: DescriptionLVPECL Output Clock Oscillator, 521MHz Nom, ROHS COMPLIANT, SMD, 6 PIN; CategoryPassive components oscillator; File Size215KB，12 Pages; ManufacturerSilicon Laboratories Inc; Environmental Compliance

Download Datasheet Parametric View All

530AB521M000DGR Overview

LVPECL Output Clock Oscillator, 521MHz Nom, ROHS COMPLIANT, SMD, 6 PIN

530AB521M000DGR Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	Silicon Laboratories Inc
package instruction	ROHS COMPLIANT, SMD, 6 PIN
Reach Compliance Code	unknown
Other features	TAPE AND REEL
maximum descent time	0.35 ns
Frequency Adjustment - Mechanical	NO
frequency stability	20%
JESD-609 code	e4
Manufacturer's serial number	530
Installation features	SURFACE MOUNT
Nominal operating frequency	521 MHz
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Oscillator type	LVPECL
physical size	7.0mm x 5.0mm x 1.85mm
longest rise time	0.35 ns
Maximum supply voltage	3.63 V
Minimum supply voltage	2.97 V
Nominal supply voltage	3.3 V
surface mount	YES
maximum symmetry	55/45 %
Terminal surface	Nickel/Gold (Ni/Au)

Preview

Download Datasheet

View All

S i 5 3 0 / 5 31

EVISION

R Y S TA L

S C I L L A T O R

(XO)

(10 M H

Z T O

1.4 G H

)

Features

Available with any-rate output

frequencies from 10 MHz to 945 MHz

and select frequencies to 1.4 GHz

3rd generation DSPLL

with superior

jitter performance

3x better frequency stability than

SAW-based oscillators

Internal fixed crystal frequency

ensures high reliability and low

aging

Available CMOS, LVPECL,

LVDS, and CML outputs

3.3, 2.5, and 1.8 V supply options

Industry-standard 5 x 7 mm

package and pinout

Pb-free/RoHS-compliant

Si5602

Ordering Information:

See page 7.

Applications

SONET/SDH

Networking

SD/HD video

Test and measurement

Clock and data recovery

FPGA/ASIC clock generation

Pin Assignments:

See page 6.

(Top View)

GND

Description

The Si530/531 XO utilizes Silicon Laboratories’ advanced DSPLL circuitry

to provide a low jitter clock at high frequencies. The Si530/531 is available

with any-rate output frequency from 10 to 945 MHz and select frequencies to

1400 MHz. Unlike a traditional XO, where a different crystal is required for

each output frequency, the Si530/531 uses one fixed crystal to provide a

wide range of output frequencies. This IC based approach allows the crystal

resonator to provide exceptional frequency stability and reliability. In addition,

DSPLL clock synthesis provides superior supply noise rejection, simplifying

the task of generating low jitter clocks in noisy environments typically found in

communication systems. The Si530/531 IC based XO is factory configurable

for a wide variety of user specifications including frequency, supply voltage,

output format, and temperature stability. Specific configurations are factory

programmed at time of shipment, thereby eliminating long lead times

associated with custom oscillators.

CLK–

CLK+

Si530 (LVDS/LVPECL/CML)

GND

Functional Block Diagram

CLK– CLK+

CLK

Si530 (CMOS)

Fixed

Frequency

Any-rate

10–1400 MHz

DSPLL

Clock

Synthesis

GND

CLK–

CLK+

Si531 (LVDS/LVPECL/CML)

GND

Rev. 1.1 6/07

Si530/531

Recommended Resources

Circuit diagram of using SK-IV's voice-activated automatic lighting to accompany music

Thermistor bias amplifier circuit

Current fed push-pull inverter circuit diagram

C523 double column vertical lathe control circuit 03

TP-8CB type 10W FM speaker circuit diagram

Simple and universal infrared remote control receiving circuit

ARM's strategic layout in the field of Internet of Things: [i=s] This post was last posted by fish001 on 2019-1-10 22:04 Edit [/i] [size=4] As the shipment of ARM chips increases, the confident ARM company's strategy and ambition to unify the software and har...; fish001 Microcontroller MCU

BearPi-HM Nano Development Board Review 1 Getting Started with Program Development: [i=s]This post was last edited by symic on 2022-3-31 00:08[/i]After a period of exploration, I was ready to start the program development based on BearPi-HM Nano. I downloaded the source code of BearP...; symic Linux and Android

Tips to effectively reduce conducted radiation interference: [b][size=4]Tips for effectively reducing conducted and radiated interference [/size][/b][color=#555555][align=left][b][size=3]Author: TI engineer Vental Mao [/size][/b][/align][align=left][size=4]Elec...; okhxyyo Analogue and Mixed Signal

Why is the output of the FIR filter core in Quartus II all zero?: I called a fir core, but why is there output only when the parallel structure is used, but no output for other types?...; my_style FPGA/CPLD

[Experts] Cannot download the program: I'm using Windows 8.1. I previously ran XP in a virtual machine to install the USB-MSP430UIF driver, and then ran CCS5.1. The first time I downloaded it, it prompted me to upgrade the firmware, and th...; 两个人的烟火 Microcontroller MCU

IIC communication slave device does not return answer signal: Use 430 I/O port to simulate IIC communication, BQ20Z75 as slave device, the simulation bus program has been practiced before and has been ensured to be correct. Now it is just a simple call to the bu...; chen502 Microcontroller MCU

Shortcut: A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF AG AH AI AJ AK AL AM AN AO AP AQ AR AS AT AU AV AW AX AY AZ B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE BF BG BH BI BJ BK BL BM BN BO BP BQ BR BS BT BU BV BW BX BY BZ C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF CG CH CI CJ CK CL CM CN CO CP CQ CR CS CT CU CV CW CX CY CZ D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF DG DH DI DJ DK DL DM DN DO DP DQ DR DS DT DU DV DW DX DZ

Popular Components