530QC1087M00DG datasheet, PDF - EEWORLD Datasheet

Datasheet> All Categories > Passive components> oscillator> 530QC1087M00DG

530QC1087M00DG: DescriptionCMOS/TTL Output Clock Oscillator, 1087MHz Nom, ROHS COMPLIANT, SMD, 6 PIN; CategoryPassive components oscillator; File Size215KB，12 Pages; ManufacturerSilicon Laboratories Inc; Environmental Compliance

Download Datasheet Parametric View All

530QC1087M00DG Overview

CMOS/TTL Output Clock Oscillator, 1087MHz Nom, ROHS COMPLIANT, SMD, 6 PIN

530QC1087M00DG Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	Silicon Laboratories Inc
package instruction	ROHS COMPLIANT, SMD, 6 PIN
Reach Compliance Code	unknown
Other features	TRAY
maximum descent time	0.35 ns
Frequency Adjustment - Mechanical	NO
frequency stability	7%
JESD-609 code	e4
Manufacturer's serial number	530
Installation features	SURFACE MOUNT
Nominal operating frequency	1087 MHz
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Oscillator type	CMOS/TTL
physical size	7.0mm x 5.0mm x 1.85mm
longest rise time	0.35 ns
Maximum supply voltage	3.63 V
Minimum supply voltage	2.97 V
Nominal supply voltage	3.3 V
surface mount	YES
maximum symmetry	55/45 %
Terminal surface	Nickel/Gold (Ni/Au)

Preview

Download Datasheet

View All

S i 5 3 0 / 5 31

EVISION

R Y S TA L

S C I L L A T O R

(XO)

(10 M H

Z T O

1.4 G H

)

Features

Available with any-rate output

frequencies from 10 MHz to 945 MHz

and select frequencies to 1.4 GHz

3rd generation DSPLL

with superior

jitter performance

3x better frequency stability than

SAW-based oscillators

Internal fixed crystal frequency

ensures high reliability and low

aging

Available CMOS, LVPECL,

LVDS, and CML outputs

3.3, 2.5, and 1.8 V supply options

Industry-standard 5 x 7 mm

package and pinout

Pb-free/RoHS-compliant

Si5602

Ordering Information:

See page 7.

Applications

SONET/SDH

Networking

SD/HD video

Test and measurement

Clock and data recovery

FPGA/ASIC clock generation

Pin Assignments:

See page 6.

(Top View)

GND

Description

The Si530/531 XO utilizes Silicon Laboratories’ advanced DSPLL circuitry

to provide a low jitter clock at high frequencies. The Si530/531 is available

with any-rate output frequency from 10 to 945 MHz and select frequencies to

1400 MHz. Unlike a traditional XO, where a different crystal is required for

each output frequency, the Si530/531 uses one fixed crystal to provide a

wide range of output frequencies. This IC based approach allows the crystal

resonator to provide exceptional frequency stability and reliability. In addition,

DSPLL clock synthesis provides superior supply noise rejection, simplifying

the task of generating low jitter clocks in noisy environments typically found in

communication systems. The Si530/531 IC based XO is factory configurable

for a wide variety of user specifications including frequency, supply voltage,

output format, and temperature stability. Specific configurations are factory

programmed at time of shipment, thereby eliminating long lead times

associated with custom oscillators.

CLK–

CLK+

Si530 (LVDS/LVPECL/CML)

GND

Functional Block Diagram

CLK– CLK+

CLK

Si530 (CMOS)

Fixed

Frequency

Any-rate

10–1400 MHz

DSPLL

Clock

Synthesis

GND

CLK–

CLK+

Si531 (LVDS/LVPECL/CML)

GND

Rev. 1.1 6/07

Si530/531

Recommended Resources

Squelch Tuned Audio Switching/Mixing Circuit Diagram

Voltage controlled oscillation generator circuit with output signal frequency range 10 to 10kHz

15W×2 high quality stereo amplifier circuit with corrected preamplifier

Simple and practical motor protection circuit

Astable flash circuit

Hatchery breeding temperature control circuit

Comparison between ARM interrupt mode (IRQ) and fast interrupt mode (FIQ): [b][color=#009900]Concepts[/color] [/b][hr] [b]IRQ[/b](Interrupt Request): refers to the interrupt mode. [b]FIQ[/b](Fast Interrupt Request): refers to the fast interrupt mode. [b]IRQ[/b] and [b]FIQ[/b...; 白丁 ARM Technology

Share: Face recognition design paper based on DSP: [color=#252525]Design paper of face recognition based on DSP[/color] [color=#252525] [/color] [color=#252525][/color] [color=#252525][/color] [color=#252525] [/color]...; Jacktang Microcontroller MCU

【Design Tools】Xilinx's new FPGA design tool makes FPGA reprogrammable: Xilinx has launched a new version of real-time debugging and verification software for FPGA designs. The company's ChipScope Pro 6.2i makes FPGA reprogrammable, and debugging of logic and embedded sys...; hangsky FPGA/CPLD

Domestic designhouse list: [i=s]This post was last edited by jameswangsynnex on 2015-3-3 20:00[/i] Please continue to add and I will compile a list. 1. Domestic TV Design Houses: In Shanghai, there are Panorama, Chip, Inno, pix...; maker Mobile and portable

LED magic stick design: [i=s]This post was last edited by paulhyde on 2014-9-15 09:06[/i] [b][font=Times New Roman]I found a design task on the Internet. Let's discuss it together! [/font][/b] [b] [/b][b][font=宋体]1. Design T...; submars Electronics Design Contest

~ccs always prompts debug assertion failed: ~ccs always prompts debug assertion failed. How do you solve it?...; huyu0427 DSP and ARM Processors

Shortcut: A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF AG AH AI AJ AK AL AM AN AO AP AQ AR AS AT AU AV AW AX AY AZ B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE BF BG BH BI BJ BK BL BM BN BO BP BQ BR BS BT BU BV BW BX BY BZ C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF CG CH CI CJ CK CL CM CN CO CP CQ CR CS CT CU CV CW CX CY CZ D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF DG DH DI DJ DK DL DM DN DO DP DQ DR DS DT DU DV DW DX DZ

Popular Components