530MB1101M00BG datasheet, PDF - EEWORLD Datasheet

Datasheet> All Categories > Passive components> oscillator> 530MB1101M00BG

530MB1101M00BG: DescriptionLVPECL Output Clock Oscillator, 1101MHz Nom, ROHS COMPLIANT, SMD, 6 PIN; CategoryPassive components oscillator; File Size268KB，15 Pages; ManufacturerSilicon Laboratories Inc; Environmental Compliance

Download Datasheet Parametric View All

530MB1101M00BG Overview

LVPECL Output Clock Oscillator, 1101MHz Nom, ROHS COMPLIANT, SMD, 6 PIN

530MB1101M00BG Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	Silicon Laboratories Inc
Reach Compliance Code	unknown
Other features	TRAY
maximum descent time	0.35 ns
Frequency Adjustment - Mechanical	NO
frequency stability	20%
JESD-609 code	e4
Manufacturer's serial number	530
Installation features	SURFACE MOUNT
Nominal operating frequency	1101 MHz
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Oscillator type	LVPECL
physical size	7.0mm x 5.0mm x 1.85mm
longest rise time	0.35 ns
Maximum supply voltage	3.63 V
Minimum supply voltage	2.97 V
Nominal supply voltage	3.3 V
surface mount	YES
maximum symmetry	55/45 %
Terminal surface	Nickel/Gold (Ni/Au)

Preview

Download Datasheet

View All

S i 5 3 0 / 5 31

R Y S TA L

S C I L L A T O R

(XO)

(10 M H

Z T O

1.4 G H

)

Features

Available with any-rate output

frequencies from 10 MHz to 945 MHz

and select frequencies to 1.4 GHz

3rd generation DSPLL

with superior

jitter performance

3x better frequency stability than

SAW-based oscillators

Internal fixed crystal frequency

ensures high reliability and low

aging

Available CMOS, LVPECL,

LVDS, and CML outputs

3.3, 2.5, and 1.8 V supply options

Industry-standard 5 x 7 mm

package and pinout

Pb-free/RoHS-compliant

Si5602

Ordering Information:

See page 7.

Applications

SONET/SDH

Networking

SD/HD video

Test and measurement

Clock and data recovery

FPGA/ASIC clock generation

Pin Assignments:

See page 6.

(Top View)

GND

Description

The Si530/531 XO utilizes Silicon Laboratories’ advanced DSPLL circuitry

to provide a low jitter clock at high frequencies. The Si530/531 is available

with any-rate output frequency from 10 to 945 MHz and select frequencies to

1400 MHz. Unlike a traditional XO, where a different crystal is required for

each output frequency, the Si530/531 uses one fixed crystal to provide a

wide range of output frequencies. This IC based approach allows the crystal

resonator to provide exceptional frequency stability and reliability. In addition,

DSPLL clock synthesis provides superior supply noise rejection, simplifying

the task of generating low jitter clocks in noisy environments typically found in

communication systems. The Si530/531 IC based XO is factory configurable

for a wide variety of user specifications including frequency, supply voltage,

output format, and temperature stability. Specific configurations are factory

programmed at time of shipment, thereby eliminating long lead times

associated with custom oscillators.

CLK–

CLK+

Si530 (LVDS/LVPECL/CML)

GND

Functional Block Diagram

CLK– CLK+

CLK

Si530 (CMOS)

Fixed

Frequency

Any-rate

10–1400 MHz

DSPLL

Clock

Synthesis

GND

CLK–

CLK+

Si531 (LVDS/LVPECL/CML)

GND

Rev. 1.0 7/06

Si530/531

Recommended Resources

Expansion circuit 1 of analog multi-way switch CD4051

Heavy load starting thermal relay protection circuit 2

Ultrasonic remote control delay light switch circuit

Voltage polarity conversion circuit

Charger circuit diagram using thyristor

Toy model road sign indicating circuit

24-bit A/D Converter CS5532 and Its Application: CS5532 is a low-noise 24-bit △-∑ type A/D converter. This paper describes in detail the structure, composition, functional characteristics and working mode of CS5532, and uses high-precision......; zzzzer16 Analog electronics

I am a high frequency person, I would like to recommend a high frequency group, welcome to join the discussion: [i=s]This post was last edited by paulhyde on 2014-9-15 09:06[/i] 89789552...; 鉴主13楼 Electronics Design Contest

How to configure registers for audio sampling chip using stm32f411 microcontroller: I am an FPGA developer. However, when using FPGA to configure the audio sampling chip tlv32, I need to use stm32f411 to configure the sampling chip using the i2c bus protocol. I don't know how to conf...; whllieying stm32/stm8

Wireless camera components: Keywords: Wireless camera consists of two parts: video circuit and audio circuit. The video part mainly consists of optical system, camera device, preamplifier, synchronous scanning system, control sy...; gzycxfj Industrial Control Electronics

Please explain why AVRMega128 accesses DS3231SN data incorrectly: I recently built a board and used Mega128 to access DS3231SN, but the data read is always 0. I don't know why. Please help me look at the code and see where the problem is. Thank you. The pull-up resi...; doleph Microchip MCU

Recommended FPGA Learning Resources (XII) - CPLD/FPGA Common Modules and Integrated System Design Examples: : [align=center][font=宋体][size=4][b]FPGA Essence Learning Resource Recommendation (Twelve) --[/b][/size][/font][color=rgb(0, 0, 0)][backcolor=rgb(237, 235, 235)][font=微软雅黑][size=18px]CPLD／FPGA Common ...; tiankai001 Download Centre

Shortcut: E0 E1 E2 E3 E4 E5 E6 E7 E8 E9 EA EB EC ED EE EF EG EH EI EJ EK EL EM EN EO EP EQ ER ES ET EU EV EW EX EY EZ F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 FA FB FC FD FE FF FG FH FI FJ FK FL FM FN FO FP FQ FR FS FT FU FV FW FX FY FZ G0 G1 G2 G3 G4 G5 G6 G7 G8 G9 GA GB GC GD GE GF GG GH GI GJ GK GL GM GN GO GP GQ GR GS GT GU GV GW GX GZ H0 H1 H2 H3 H4 H5 H6 H7 H8 HA HB HC HD HE HF HG HH HI HJ HK HL HM HN HO HP HQ HR HS HT HU HV HW HX HY HZ I1 I2 I3 I4 I5 I6 I7 IA IB IC ID IE IF IG IH II IK IL IM IN IO IP IQ IR IS IT IU IV IW IX J0 J1 J2 J6 J7 JA JB JC JD JE JF JG JH JJ JK JL JM JN JP JQ JR JS JT JV JW JX JZ K0 K1 K2 K3 K4 K5 K6 K7 K8 K9 KA KB KC KD KE KF KG KH KI KJ KK KL KM KN KO KP KQ KR KS KT KU KV KW KX KY KZ

Popular Components