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533ACFREQDG

Description
LVPECL Output Clock Oscillator, 10MHz Min, 945MHz Max, ROHS COMPLIANT PACKAGE-6
CategoryPassive components    oscillator   
File Size225KB,12 Pages
ManufacturerSilicon Laboratories Inc
Environmental Compliance
Download Datasheet Parametric View All

533ACFREQDG Overview

LVPECL Output Clock Oscillator, 10MHz Min, 945MHz Max, ROHS COMPLIANT PACKAGE-6

533ACFREQDG Parametric

Parameter NameAttribute value
Is it Rohs certified?conform to
MakerSilicon Laboratories Inc
Reach Compliance Codeunknown
Other featuresTRISTATE; ENABLE/DISABLE FUNCTION; TRAY
maximum descent time0.35 ns
Frequency Adjustment - MechanicalNO
frequency stability7%
Installation featuresSURFACE MOUNT
Maximum operating frequency945 MHz
Minimum operating frequency10 MHz
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
Oscillator typeLVPECL
physical size7.0mm x 5.0mm x 0.6mm
longest rise time0.35 ns
Maximum supply voltage3.63 V
Minimum supply voltage2.97 V
Nominal supply voltage3.3 V
surface mountYES
maximum symmetry55/45 %
Si533
R
EVISION
D
D
U A L
F
R E Q U E N C Y
C
R Y S TA L
O
S C I L L A T O R
(XO )
(10 M H
Z T O
1.4 G H
Z
)
Features
Available with any-rate output
frequencies from 10 MHz to 945 MHz
and select frequencies to 1.4 GHz
2 selectable output frequencies
3rd generation DSPLL
®
with superior
jitter performance
3x better frequency stability than
SAW-based oscillators
Pin 1 output enable (OE)
Internal fixed crystal frequency
ensures high reliability and low
aging
Available CMOS, LVPECL,
LVDS, and CML outputs
3.3, 2.5, and 1.8 V supply options
Industry-standard 5 x 7 mm
package and pinout
Pb-free/RoHS-compliant
Si5602
Applications
SONET/SDH
Networking
SD/HD video
Clock and data recovery
FPGA/ASIC clock generation
Ordering Information:
See page 7.
Description
The Si533 dual frequency XO utilizes Silicon Laboratories’ advanced
DSPLL
®
circuitry to provide a low jitter clock at high frequencies. The Si533
is available with any-rate output frequency from 10 to 945 MHz and select
frequencies to 1400 MHz. Unlike a traditional XO, where a different crystal is
required for each output frequency, the Si533 uses one fixed crystal to
provide a wide range of output frequencies. This IC based approach allows
the crystal resonator to provide exceptional frequency stability and reliability.
In addition, DSPLL clock synthesis provides superior supply noise rejection,
simplifying the task of generating low jitter clocks in noisy environments
typically found in communication systems. The Si533 IC based XO is factory
configurable for a wide variety of user specifications including frequency,
supply voltage, output format, and temperature stability. Specific
configurations are factory programmed at time of shipment, thereby
eliminating long lead times associated with custom oscillators.
Pin Assignments:
See page 6.
(Top View)
OE
FS
GND
1
2
3
6
5
4
V
DD
CLK–
CLK+
LVDS/LVPECL/CML
Functional Block Diagram
V
DD
CLK– CLK+
OE
FS
1
2
3
CMOS
6
5
4
V
DD
NC
CLK+
Fixed
Frequency
XO
Any-rate
10–1400 MHz
DSPLL®
Clock
Synthesis
GND
OE
FS
GND
Rev. 1.1 6/07
Copyright © 2007 by Silicon Laboratories
Si533
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