531MB1068M00BGR datasheet, PDF

Datasheet> All Categories > Passive components> oscillator> 531MB1068M00BGR

531MB1068M00BGR: DescriptionLVPECL Output Clock Oscillator, 1068MHz Nom, ROHS COMPLIANT, SMD, 6 PIN; CategoryPassive components oscillator; File Size268KB，15 Pages; ManufacturerSilicon Laboratories Inc; Environmental Compliance

Download Datasheet Parametric View All

531MB1068M00BGR Overview

LVPECL Output Clock Oscillator, 1068MHz Nom, ROHS COMPLIANT, SMD, 6 PIN

531MB1068M00BGR Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	Silicon Laboratories Inc
Reach Compliance Code	unknown
Other features	TAPE AND REEL
maximum descent time	0.35 ns
Frequency Adjustment - Mechanical	NO
frequency stability	20%
JESD-609 code	e4
Manufacturer's serial number	531
Installation features	SURFACE MOUNT
Nominal operating frequency	1068 MHz
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Oscillator type	LVPECL
physical size	7.0mm x 5.0mm x 1.85mm
longest rise time	0.35 ns
Maximum supply voltage	3.63 V
Minimum supply voltage	2.97 V
Nominal supply voltage	3.3 V
surface mount	YES
maximum symmetry	55/45 %
Terminal surface	Nickel/Gold (Ni/Au)

Preview

Download Datasheet

View All

S i 5 3 0 / 5 31

R Y S TA L

S C I L L A T O R

(XO)

(10 M H

Z T O

1.4 G H

)

Features

Available with any-rate output

frequencies from 10 MHz to 945 MHz

and select frequencies to 1.4 GHz

3rd generation DSPLL

with superior

jitter performance

3x better frequency stability than

SAW-based oscillators

Internal fixed crystal frequency

ensures high reliability and low

aging

Available CMOS, LVPECL,

LVDS, and CML outputs

3.3, 2.5, and 1.8 V supply options

Industry-standard 5 x 7 mm

package and pinout

Pb-free/RoHS-compliant

Si5602

Ordering Information:

See page 7.

Applications

SONET/SDH

Networking

SD/HD video

Test and measurement

Clock and data recovery

FPGA/ASIC clock generation

Pin Assignments:

See page 6.

(Top View)

GND

Description

The Si530/531 XO utilizes Silicon Laboratories’ advanced DSPLL circuitry

to provide a low jitter clock at high frequencies. The Si530/531 is available

with any-rate output frequency from 10 to 945 MHz and select frequencies to

1400 MHz. Unlike a traditional XO, where a different crystal is required for

each output frequency, the Si530/531 uses one fixed crystal to provide a

wide range of output frequencies. This IC based approach allows the crystal

resonator to provide exceptional frequency stability and reliability. In addition,

DSPLL clock synthesis provides superior supply noise rejection, simplifying

the task of generating low jitter clocks in noisy environments typically found in

communication systems. The Si530/531 IC based XO is factory configurable

for a wide variety of user specifications including frequency, supply voltage,

output format, and temperature stability. Specific configurations are factory

programmed at time of shipment, thereby eliminating long lead times

associated with custom oscillators.

CLK–

CLK+

Si530 (LVDS/LVPECL/CML)

GND

Functional Block Diagram

CLK– CLK+

CLK

Si530 (CMOS)

Fixed

Frequency

Any-rate

10–1400 MHz

DSPLL

Clock

Synthesis

GND

CLK–

CLK+

Si531 (LVDS/LVPECL/CML)

GND

Rev. 1.0 7/06

Si530/531

Recommended Resources

Message controller that replaces phone ringtones with voice

Constant current charging circuit

Equivalent circuit diagram of PSD

Electrical schematic diagram of M7120 surface grinder (1)

Circuit diagram of low-power low-frequency amplifier using binary numbers to control gain

555 long delay timer circuit diagram 2

Who can help me analyze the scan function of this matrix keyboard. I can't understand the last sentence: #include #define uint unsigned int #define uchar unsigned char uchar code tab[]={0xee,0xed,0xeb,0xe7, 0xde,0xdd,0xdb,0xd7, 0xbe,0xbd,0xbb,0xb7, 0x7e,0x7d,0x7b,0x77,} ; uchar code tab1[]={0x88,0Xbe,0Xc...; cf2928 MCU

Multiple wire variable summation problem: Does anyone know how to simplify the Verilog programming of summing multiple variables? The output is wire. Now I have to input them one by one, which is too troublesome. The program is as follows: [c...; collinsw FPGA/CPLD

2013 Topic: [i=s]This post was last edited by paulhyde on 2014-9-15 03:02[/i] 2013 topic! Good luck everyone!...; yehen0611 Electronics Design Contest

Logic Analyzer Basics: Oscilloscopes with integrated logic analyzers are very popular now. I think they are very useful if they are paired with powerful host computer software. The oscilloscope is only responsible for colle...; qq849682862 Test/Measurement

How to develop wince6.0 dsplink program under vs2005?: My development environment is vs2005, and I have installed the sdk with dsplink. Now I want to use dsplink api when developing wince6.0 program, how should I configure vs2005?ps: I configured it like ...; liusum Embedded System

Overall design of wireless sensor network nodes: [size=4] Wireless Sensor Networks (WSNs) are composed of a large number of cheap micro sensor nodes deployed in the monitoring area. Through wireless communication, they form a multi-hop self-organizi...; Aguilera Wireless Connectivity

Shortcut: A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF AG AH AI AJ AK AL AM AN AO AP AQ AR AS AT AU AV AW AX AY AZ B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE BF BG BH BI BJ BK BL BM BN BO BP BQ BR BS BT BU BV BW BX BY BZ C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF CG CH CI CJ CK CL CM CN CO CP CQ CR CS CT CU CV CW CX CY CZ D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF DG DH DI DJ DK DL DM DN DO DP DQ DR DS DT DU DV DW DX DZ

Popular Components