531DC1287M00DG datasheet, PDF - EEWORLD Datasheet

Datasheet> All Categories > Passive components> oscillator> 531DC1287M00DG

531DC1287M00DG: DescriptionCMOS/TTL Output Clock Oscillator, 1287MHz Nom, ROHS COMPLIANT, SMD, 6 PIN; CategoryPassive components oscillator; File Size215KB，12 Pages; ManufacturerSilicon Laboratories Inc; Environmental Compliance

Download Datasheet Parametric View All

531DC1287M00DG Overview

CMOS/TTL Output Clock Oscillator, 1287MHz Nom, ROHS COMPLIANT, SMD, 6 PIN

531DC1287M00DG Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	Silicon Laboratories Inc
Reach Compliance Code	unknown
Other features	TRAY
maximum descent time	0.35 ns
Frequency Adjustment - Mechanical	NO
frequency stability	7%
JESD-609 code	e4
Manufacturer's serial number	531
Installation features	SURFACE MOUNT
Nominal operating frequency	1287 MHz
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Oscillator type	CMOS/TTL
physical size	7.0mm x 5.0mm x 1.85mm
longest rise time	0.35 ns
Maximum supply voltage	3.63 V
Minimum supply voltage	2.97 V
Nominal supply voltage	3.3 V
surface mount	YES
maximum symmetry	55/45 %
Terminal surface	Nickel/Gold (Ni/Au)

Preview

Download Datasheet

View All

S i 5 3 0 / 5 31

EVISION

R Y S TA L

S C I L L A T O R

(XO)

(10 M H

Z T O

1.4 G H

)

Features

Available with any-rate output

frequencies from 10 MHz to 945 MHz

and select frequencies to 1.4 GHz

3rd generation DSPLL

with superior

jitter performance

3x better frequency stability than

SAW-based oscillators

Internal fixed crystal frequency

ensures high reliability and low

aging

Available CMOS, LVPECL,

LVDS, and CML outputs

3.3, 2.5, and 1.8 V supply options

Industry-standard 5 x 7 mm

package and pinout

Pb-free/RoHS-compliant

Si5602

Ordering Information:

See page 7.

Applications

SONET/SDH

Networking

SD/HD video

Test and measurement

Clock and data recovery

FPGA/ASIC clock generation

Pin Assignments:

See page 6.

(Top View)

GND

Description

The Si530/531 XO utilizes Silicon Laboratories’ advanced DSPLL circuitry

to provide a low jitter clock at high frequencies. The Si530/531 is available

with any-rate output frequency from 10 to 945 MHz and select frequencies to

1400 MHz. Unlike a traditional XO, where a different crystal is required for

each output frequency, the Si530/531 uses one fixed crystal to provide a

wide range of output frequencies. This IC based approach allows the crystal

resonator to provide exceptional frequency stability and reliability. In addition,

DSPLL clock synthesis provides superior supply noise rejection, simplifying

the task of generating low jitter clocks in noisy environments typically found in

communication systems. The Si530/531 IC based XO is factory configurable

for a wide variety of user specifications including frequency, supply voltage,

output format, and temperature stability. Specific configurations are factory

programmed at time of shipment, thereby eliminating long lead times

associated with custom oscillators.

CLK–

CLK+

Si530 (LVDS/LVPECL/CML)

GND

Functional Block Diagram

CLK– CLK+

CLK

Si530 (CMOS)

Fixed

Frequency

Any-rate

10–1400 MHz

DSPLL

Clock

Synthesis

GND

CLK–

CLK+

Si531 (LVDS/LVPECL/CML)

GND

Rev. 1.1 6/07

Si530/531

Recommended Resources

What are the hot spots in integrated circuit research?

LB1475 (video recorder) two-wire wired remote control circuit

Radio car finder circuit

Circuit diagram for arbitrarily setting the backup power supply voltage

Positive and negative reference voltage source circuit diagram using op amp

Schematic diagram of boost chopper switching regulated power supply

[I contribute to the XILINX Resource Center] Xilinx FPGA implements software DA output sine wave through PWM: Xilinx FPGA implements software DA output sine wave through PWM...; wanghongyang FPGA/CPLD

Frequency Converters and Mixers: [color=#000][font=verdana, sans-serif][size=4][b]1. What is a frequency converter? [/b][/size][/font][/color] [color=#000][font=verdana, sans-serif] 1. A variable-frequency drive (VFD) is a power cont...; Jacktang Analogue and Mixed Signal

EEWORLD University Hall ---- Accelerate FPGA power supply design: Accelerating FPGA Power Supply Design : https://training.eeworld.com.cn/course/2106Accelerate FPGA Power Supply Design...; chenyy Power technology

Application Guide for HB6296 High Voltage and High Current Charging Management Chip for 2-10 Cells Lithium Battery 24V Lead Acid: HB6296 Application Guide1. Wiring: A: The current detection resistor is placed close to the hb6296 . The voltage signal on the detection resistor is very weak. To reduce interference, it must be place...; htdzxiaoyao Power technology

Schematic diagram - Can the push-pull circuit in this place be omitted?: The circuit diagram is as follows:Load B1 is a motor. U1C is a comparator. I want to ask whether this push-pull circuit is necessary? If we don't want a push-pull circuit, is it possible to connect th...; 普拉卡图 Analog electronics

GPS/gprs module general input and output issues: Has anyone used GPS/GPRS module? How do such modules generally communicate? How many inputs and outputs are there? What are the signals?...; 安_然 Analog electronics

Shortcut: E0 E1 E2 E3 E4 E5 E6 E7 E8 E9 EA EB EC ED EE EF EG EH EI EJ EK EL EM EN EO EP EQ ER ES ET EU EV EW EX EY EZ F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 FA FB FC FD FE FF FG FH FI FJ FK FL FM FN FO FP FQ FR FS FT FU FV FW FX FY FZ G0 G1 G2 G3 G4 G5 G6 G7 G8 G9 GA GB GC GD GE GF GG GH GI GJ GK GL GM GN GO GP GQ GR GS GT GU GV GW GX GZ H0 H1 H2 H3 H4 H5 H6 H7 H8 HA HB HC HD HE HF HG HH HI HJ HK HL HM HN HO HP HQ HR HS HT HU HV HW HX HY HZ I1 I2 I3 I4 I5 I6 I7 IA IB IC ID IE IF IG IH II IK IL IM IN IO IP IQ IR IS IT IU IV IW IX J0 J1 J2 J6 J7 JA JB JC JD JE JF JG JH JJ JK JL JM JN JP JQ JR JS JT JV JW JX JZ K0 K1 K2 K3 K4 K5 K6 K7 K8 K9 KA KB KC KD KE KF KG KH KI KJ KK KL KM KN KO KP KQ KR KS KT KU KV KW KX KY KZ

Popular Components