EEWORLDEEWORLDEEWORLD

Part Number

Search

531NA717M000DGR

Description
LVDS Output Clock Oscillator, 717MHz Nom, ROHS COMPLIANT, SMD, 6 PIN
CategoryPassive components    oscillator   
File Size215KB,12 Pages
ManufacturerSilicon Laboratories Inc
Environmental Compliance  
Download Datasheet Parametric View All

531NA717M000DGR Overview

LVDS Output Clock Oscillator, 717MHz Nom, ROHS COMPLIANT, SMD, 6 PIN

531NA717M000DGR Parametric

Parameter NameAttribute value
Is it lead-free?Lead free
Is it Rohs certified?conform to
MakerSilicon Laboratories Inc
Reach Compliance Codeunknown
Other featuresTAPE AND REEL
maximum descent time0.35 ns
Frequency Adjustment - MechanicalNO
frequency stability50%
JESD-609 codee4
Manufacturer's serial number531
Installation featuresSURFACE MOUNT
Nominal operating frequency717 MHz
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
Oscillator typeLVDS
physical size7.0mm x 5.0mm x 1.85mm
longest rise time0.35 ns
Maximum supply voltage3.63 V
Minimum supply voltage2.97 V
Nominal supply voltage3.3 V
surface mountYES
maximum symmetry55/45 %
Terminal surfaceNickel/Gold (Ni/Au)
S i 5 3 0 / 5 31
R
EVISION
D
C
R Y S TA L
O
S C I L L A T O R
(XO)
(10 M H
Z T O
1.4 G H
Z
)
Features
Available with any-rate output
frequencies from 10 MHz to 945 MHz
and select frequencies to 1.4 GHz
3rd generation DSPLL
®
with superior
jitter performance
3x better frequency stability than
SAW-based oscillators
Internal fixed crystal frequency
ensures high reliability and low
aging
Available CMOS, LVPECL,
LVDS, and CML outputs
3.3, 2.5, and 1.8 V supply options
Industry-standard 5 x 7 mm
package and pinout
Pb-free/RoHS-compliant
Si5602
Ordering Information:
See page 7.
Applications
SONET/SDH
Networking
SD/HD video
Test and measurement
Clock and data recovery
FPGA/ASIC clock generation
Pin Assignments:
See page 6.
(Top View)
NC
OE
GND
1
2
3
6
5
4
V
DD
Description
The Si530/531 XO utilizes Silicon Laboratories’ advanced DSPLL circuitry
to provide a low jitter clock at high frequencies. The Si530/531 is available
with any-rate output frequency from 10 to 945 MHz and select frequencies to
1400 MHz. Unlike a traditional XO, where a different crystal is required for
each output frequency, the Si530/531 uses one fixed crystal to provide a
wide range of output frequencies. This IC based approach allows the crystal
resonator to provide exceptional frequency stability and reliability. In addition,
DSPLL clock synthesis provides superior supply noise rejection, simplifying
the task of generating low jitter clocks in noisy environments typically found in
communication systems. The Si530/531 IC based XO is factory configurable
for a wide variety of user specifications including frequency, supply voltage,
output format, and temperature stability. Specific configurations are factory
programmed at time of shipment, thereby eliminating long lead times
associated with custom oscillators.
®
CLK–
CLK+
Si530 (LVDS/LVPECL/CML)
OE
NC
GND
1
2
3
6
5
4
V
DD
Functional Block Diagram
V
DD
CLK– CLK+
NC
CLK
Si530 (CMOS)
Fixed
Frequency
XO
Any-rate
10–1400 MHz
DSPLL
®
Clock
Synthesis
OE
NC
GND
1
2
3
6
5
4
V
DD
CLK–
CLK+
Si531 (LVDS/LVPECL/CML)
OE
GND
Rev. 1.1 6/07
Copyright © 2007 by Silicon Laboratories
Si530/531
Can I ask for the input method registration form?
I would like to ask about the input method registry. Why are some input method registries in the following format: [HKEY_LOCAL_MACHINE\System\CurrentControlSet\Control\Layouts\e0010804] "Layout Text"=...
wenwen223 Embedded System
Altium Designer 18.1.5 How to change Mechanical1 back to Keepout layer
I have to do it manually inside, which is a bit tricky. Please help me....
btty038 PCB Design
How to determine whether the received data is a command or data when FPGA controls the data transmission and reception of the network card chip
I use FPGA to control the network card chip to make a data transmission and reception device, but how can I make FPGA start sending data? Specifically, FPGA starts sending data when it receives a comm...
yyj807 FPGA/CPLD
Modify the files extracted from DSP56F803
The program read from DSP56F803BU80E is saved in BIN or S19 format. Now I want to modify some character data, but I can't find the check bit in the Hex editor. After modifying it, it can't be used whe...
56F803 NXP MCU
BK3432 SDK Development and Use GuideBK3432 SDK Development and Use Guide
BK3432 SDK Development and Use Guide BK3432 SDK Development and Use GuideLow-power BLE4.2+3.0 dual-mode chip, suitable for electronic scales, POS machines, anti-lost devices, self-timers, remote contr...
无线大师 Integrated technical exchanges
Summary of Fujitsu Industrial Measurement and Control DIY Activities
I participated in this activity with curiosity and the urge to learn about ARM. I only knew a little about 51 and obviously underestimated the complexity of ARM. Because I had never touched ARM before...
daijun DIY/Open Source Hardware

EEWorld
subscription
account

EEWorld
service
account

Automotive
development
circle

Robot
development
community

Index Files: 2853  1076  1952  2297  782  58  22  40  47  16 
Datasheet   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Room 1530, 15th Floor, Building B, No. 18 Zhongguancun Street, Haidian District, Beijing Telephone: (010) 82350740 Postal Code: 100190
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved 京ICP证060456号 京ICP备10001474号-1 电信业务审批[2006]字第258号函 京公网安备 11010802033920号