EEWORLDEEWORLDEEWORLD

Part Number

Search

530GB38M0000BGR

Description
CMOS Output Clock Oscillator, 38MHz Nom, ROHS COMPLIANT, SMD, 6 PIN
CategoryPassive components    oscillator   
File Size268KB,15 Pages
ManufacturerSilicon Laboratories Inc
Environmental Compliance  
Download Datasheet Parametric View All

530GB38M0000BGR Overview

CMOS Output Clock Oscillator, 38MHz Nom, ROHS COMPLIANT, SMD, 6 PIN

530GB38M0000BGR Parametric

Parameter NameAttribute value
Is it lead-free?Lead free
Is it Rohs certified?conform to
MakerSilicon Laboratories Inc
Reach Compliance Codeunknown
Other featuresTAPE AND REEL
Frequency Adjustment - MechanicalNO
frequency stability20%
JESD-609 codee4
Manufacturer's serial number530
Installation featuresSURFACE MOUNT
Nominal operating frequency38 MHz
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
Oscillator typeCMOS
physical size7.0mm x 5.0mm x 1.85mm
Maximum supply voltage2.75 V
Minimum supply voltage2.25 V
Nominal supply voltage2.5 V
surface mountYES
maximum symmetry55/45 %
Terminal surfaceNickel/Gold (Ni/Au)
S i 5 3 0 / 5 31
C
R Y S TA L
O
S C I L L A T O R
(XO)
(10 M H
Z T O
1.4 G H
Z
)
Features
Available with any-rate output
frequencies from 10 MHz to 945 MHz
and select frequencies to 1.4 GHz
3rd generation DSPLL
®
with superior
jitter performance
3x better frequency stability than
SAW-based oscillators
Internal fixed crystal frequency
ensures high reliability and low
aging
Available CMOS, LVPECL,
LVDS, and CML outputs
3.3, 2.5, and 1.8 V supply options
Industry-standard 5 x 7 mm
package and pinout
Pb-free/RoHS-compliant
Si5602
Ordering Information:
See page 7.
Applications
SONET/SDH
Networking
SD/HD video
Test and measurement
Clock and data recovery
FPGA/ASIC clock generation
Pin Assignments:
See page 6.
(Top View)
NC
OE
GND
1
2
3
6
5
4
V
DD
Description
The Si530/531 XO utilizes Silicon Laboratories’ advanced DSPLL circuitry
to provide a low jitter clock at high frequencies. The Si530/531 is available
with any-rate output frequency from 10 to 945 MHz and select frequencies to
1400 MHz. Unlike a traditional XO, where a different crystal is required for
each output frequency, the Si530/531 uses one fixed crystal to provide a
wide range of output frequencies. This IC based approach allows the crystal
resonator to provide exceptional frequency stability and reliability. In addition,
DSPLL clock synthesis provides superior supply noise rejection, simplifying
the task of generating low jitter clocks in noisy environments typically found in
communication systems. The Si530/531 IC based XO is factory configurable
for a wide variety of user specifications including frequency, supply voltage,
output format, and temperature stability. Specific configurations are factory
programmed at time of shipment, thereby eliminating long lead times
associated with custom oscillators.
®
CLK–
CLK+
Si530 (LVDS/LVPECL/CML)
OE
NC
GND
1
2
3
6
5
4
V
DD
Functional Block Diagram
V
DD
CLK– CLK+
NC
CLK
Si530 (CMOS)
Fixed
Frequency
XO
Any-rate
10–1400 MHz
DSPLL
®
Clock
Synthesis
OE
NC
GND
1
2
3
6
5
4
V
DD
CLK–
CLK+
Si531 (LVDS/LVPECL/CML)
OE
GND
Rev. 1.0 7/06
Copyright © 2006 by Silicon Laboratories
Si530/531
MSP430 Learning Notes VI: U-port Simulation
The kit comes with a USB emulator, but I have never dared to use it. I had some time this afternoon, so I tried it, but it was not obedient and kept sending waves. Because I couldn't respond when I si...
ddllxxrr Microcontroller MCU
Fashionable sliding cover style super Skype mouse phone is launched
We all know that Skype is a free Internet phone, which is what we often call VoIP. However, since it is a phone call, it seems that using a regular headset and microphone is not the same thing, and th...
songbo RF/Wirelessly
DSP tension, depth and speed measurement system
[i=s]This post was last edited by fish001 on 2018-11-8 23:35[/i] [size=4] During the oilfield logging process, ground operators need to know the depth of the oil well, the cable downhole speed and the...
fish001 DSP and ARM Processors
What is the clock configuration of stm32IO port?
What is the clock configuration of each IIO port of 32? After I changed the IO port of the program, I can't get the original effect. I hope all the experts can explain it to me. I will be very gratefu...
你们的富强哥哥 stm32/stm8
Four language taboos when subordinates talk with leaders
Scenario case: Xiao Xu has been working in the company for many years. She has done a lot of work and achieved a lot. However, many colleagues who joined the company at the same time have been promote...
ESD技术咨询 Talking about work
Help, about latch in SRAM design
I designed an SRAM, but it turned out to have 8 12-bit latches. I don't know how to eliminate them. I hope an expert can help me. Thanks in advance ! The code is as follows: module SRAM(CLK, CS, AWE, ...
goodsaint FPGA/CPLD

EEWorld
subscription
account

EEWorld
service
account

Automotive
development
circle

Robot
development
community

Index Files: 864  170  2571  523  1017  18  4  52  11  21 
Datasheet   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Room 1530, 15th Floor, Building B, No. 18 Zhongguancun Street, Haidian District, Beijing Telephone: (010) 82350740 Postal Code: 100190
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved 京ICP证060456号 京ICP备10001474号-1 电信业务审批[2006]字第258号函 京公网安备 11010802033920号