530AA137M000DG datasheet, PDF - EEWORLD Datasheet

Datasheet> All Categories > Passive components> oscillator> 530AA137M000DG

530AA137M000DG: DescriptionLVPECL Output Clock Oscillator, 137MHz Nom, ROHS COMPLIANT, SMD, 6 PIN; CategoryPassive components oscillator; File Size1MB，12 Pages; ManufacturerSilicon Laboratories Inc; Environmental Compliance

Download Datasheet Parametric View All

530AA137M000DG Overview

LVPECL Output Clock Oscillator, 137MHz Nom, ROHS COMPLIANT, SMD, 6 PIN

530AA137M000DG Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	Silicon Laboratories Inc
package instruction	ROHS COMPLIANT, SMD, 6 PIN
Reach Compliance Code	compliant
Other features	TRAY
maximum descent time	0.35 ns
Frequency Adjustment - Mechanical	NO
frequency stability	50%
JESD-609 code	e4
Manufacturer's serial number	530
Installation features	SURFACE MOUNT
Nominal operating frequency	137 MHz
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Oscillator type	LVPECL
physical size	7.0mm x 5.0mm x 1.85mm
longest rise time	0.35 ns
Maximum supply voltage	3.63 V
Minimum supply voltage	2.97 V
Nominal supply voltage	3.3 V
surface mount	YES
maximum symmetry	55/45 %
Terminal surface	Nickel/Gold (Ni/Au)

Preview

Download Datasheet

View All

S i 5 3 0 / 5 31

EVISION

R YS TA L

SCILLATOR

(XO) (10 M H

Features

Available with any-rate output



frequencies from 10 MHz to 945 MHz

and select frequencies to 1.4 GHz



3rd generation DSPLL

with superior



jitter performance



3x better frequency stability than



SAW-based oscillators



1.4 GH

)

Internal fixed crystal frequency

ensures high reliability and low

aging

Available CMOS, LVPECL,

LVDS, and CML outputs

3.3, 2.5, and 1.8 V supply options

Industry-standard 5 x 7 mm

package and pinout



Pb-free/RoHS-compliant

Si5602

Ordering Information:

See page 7.

Applications

SONET/SDH



Networking



SD/HD video



Test and measurement



Clock and data recovery



FPGA/ASIC clock generation



Pin Assignments:

See page 6.

(Top View)

GND

Description

The Si530/531 XO utilizes Silicon Laboratories’ advanced DSPLL circuitry

to provide a low jitter clock at high frequencies. The Si530/531 is available

with any-rate output frequency from 10 to 945 MHz and select frequencies to

1400 MHz. Unlike a traditional XO, where a different crystal is required for

each output frequency, the Si530/531 uses one fixed crystal to provide a

wide range of output frequencies. This IC based approach allows the crystal

resonator to provide exceptional frequency stability and reliability. In addition,

DSPLL clock synthesis provides superior supply noise rejection, simplifying

the task of generating low jitter clocks in noisy environments typically found in

communication systems. The Si530/531 IC based XO is factory configurable

for a wide variety of user specifications including frequency, supply voltage,

output format, and temperature stability. Specific configurations are factory

programmed at time of shipment, thereby eliminating long lead times

associated with custom oscillators.

CLK–

CLK+

Si530 (LVDS/LVPECL/CML)

GND

Functional Block Diagram

CLK– CLK+

CLK

Si530 (CMOS)

Fixed

Frequency

Any-rate

10–1400 MHz

DSPLL

Clock

Synthesis

GND

CLK–

CLK+

Si531 (LVDS/LVPECL/CML)

GND

Rev. 1.5 6/18

Si530/531

Recommended Resources

Motor automatic reciprocating control circuit

Offset Adjustment Current Source Circuit Diagram

T68 horizontal boring machine electrical schematic circuit (2)

50w ISNE541 high-fidelity amplifier circuit

How to do image processing with ARM microcontroller: rt, I'm a newbie who has just learned a little bit about microcontrollers. Now my teacher wants me to find a board that can capture images, burn the system, install opencv and vs. Please recommend and...; 高半仙 ARM Technology

Please recommend a chip with integrated Ethernet controller + PHY: What I want to do recently requires a low-cost chip that integrates an Ethernet controller and PHY. TI has quite a few LM3S chips, but I am not familiar with this series. I would like to ask you to re...; bluehacker Microcontroller MCU

Why is it so difficult to enter the learning interface?: Every time a registration page pops up, but I have already completed the registration and just want to enter the learning page...; xinxin3219 Microcontroller MCU

Several MP3 schematics collected by my buddy: I have collected several MP3 schematics, including ALIM5661X (commonly known as Ali solution)/Actions ATJ2055/ATJ2091/ATJ2135/SUNLINE SPDA1000/Rising Micro 2608A. Friends who need it can take a look. ...; 西门 Test/Measurement

The transplanted u-boot used by hl340 to usb has garbled characters: The transplanted u-boot used by hl340 to usb has garbled characters, but there is no garbled characters when directly connected to the serial port. Does hl340 not support uboot? Please tell me clearly...; tmasd Embedded System

[Low Power Consumption] FPGA/CPLD Design Experience Sharing Materials (Transferred): This article shares some basic concepts in FPGA design (such as setup time, hold time, race conditions, triggers, latches) and some design methods (such as synchronization design, delay circuit design...; dream_byxiaoyu FPGA/CPLD

Shortcut: L0 L1 L2 L3 L4 L5 L6 L7 L8 L9 LA LB LC LD LE LF LG LH LI LJ LK LL LM LN LO LP LQ LR LS LT LU LV LW LX LY LZ M0 M1 M2 M3 M4 M5 M6 M7 M8 M9 MA MB MC MD ME MF MG MH MI MJ MK ML MM MN MO MP MQ MR MS MT MU MV MW MX MY MZ N0 N1 N2 N3 N4 N5 N6 N7 N8 NA NB NC ND NE NF NG NH NI NJ NK NL NM NN NO NP NQ NR NS NT NU NV NX NZ O0 O1 O2 O3 OA OB OC OD OE OF OG OH OI OJ OK OL OM ON OP OQ OR OS OT OV OX OY OZ P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 PA PB PC PD PE PF PG PH PI PJ PK PL PM PN PO PP PQ PR PS PT PU PV PW PX PY PZ Q1 Q2 Q3 Q4 Q5 Q6 Q8 Q9 QA QB QC QE QF QG QH QK QL QM QP QR QS QT QV QW QX QY R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 RA RB RC RD RE RF RG RH RI RJ RK RL RM RN RO RP RQ RR RS RT RU RV RW RX RY RZ

Popular Components