EEWORLDEEWORLDEEWORLD

Part Number

Search

530DC842M000DG

Description
CMOS/TTL Output Clock Oscillator, 842MHz Nom, ROHS COMPLIANT, SMD, 6 PIN
CategoryPassive components    oscillator   
File Size215KB,12 Pages
ManufacturerSilicon Laboratories Inc
Environmental Compliance  
Download Datasheet Parametric View All

530DC842M000DG Overview

CMOS/TTL Output Clock Oscillator, 842MHz Nom, ROHS COMPLIANT, SMD, 6 PIN

530DC842M000DG Parametric

Parameter NameAttribute value
Is it lead-free?Lead free
Is it Rohs certified?conform to
MakerSilicon Laboratories Inc
package instructionROHS COMPLIANT, SMD, 6 PIN
Reach Compliance Codeunknown
Other featuresTRAY
maximum descent time0.35 ns
Frequency Adjustment - MechanicalNO
frequency stability7%
JESD-609 codee4
Manufacturer's serial number530
Installation featuresSURFACE MOUNT
Nominal operating frequency842 MHz
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
Oscillator typeCMOS/TTL
physical size7.0mm x 5.0mm x 1.85mm
longest rise time0.35 ns
Maximum supply voltage3.63 V
Minimum supply voltage2.97 V
Nominal supply voltage3.3 V
surface mountYES
maximum symmetry55/45 %
Terminal surfaceNickel/Gold (Ni/Au)
S i 5 3 0 / 5 31
R
EVISION
D
C
R Y S TA L
O
S C I L L A T O R
(XO)
(10 M H
Z T O
1.4 G H
Z
)
Features
Available with any-rate output
frequencies from 10 MHz to 945 MHz
and select frequencies to 1.4 GHz
3rd generation DSPLL
®
with superior
jitter performance
3x better frequency stability than
SAW-based oscillators
Internal fixed crystal frequency
ensures high reliability and low
aging
Available CMOS, LVPECL,
LVDS, and CML outputs
3.3, 2.5, and 1.8 V supply options
Industry-standard 5 x 7 mm
package and pinout
Pb-free/RoHS-compliant
Si5602
Ordering Information:
See page 7.
Applications
SONET/SDH
Networking
SD/HD video
Test and measurement
Clock and data recovery
FPGA/ASIC clock generation
Pin Assignments:
See page 6.
(Top View)
NC
OE
GND
1
2
3
6
5
4
V
DD
Description
The Si530/531 XO utilizes Silicon Laboratories’ advanced DSPLL circuitry
to provide a low jitter clock at high frequencies. The Si530/531 is available
with any-rate output frequency from 10 to 945 MHz and select frequencies to
1400 MHz. Unlike a traditional XO, where a different crystal is required for
each output frequency, the Si530/531 uses one fixed crystal to provide a
wide range of output frequencies. This IC based approach allows the crystal
resonator to provide exceptional frequency stability and reliability. In addition,
DSPLL clock synthesis provides superior supply noise rejection, simplifying
the task of generating low jitter clocks in noisy environments typically found in
communication systems. The Si530/531 IC based XO is factory configurable
for a wide variety of user specifications including frequency, supply voltage,
output format, and temperature stability. Specific configurations are factory
programmed at time of shipment, thereby eliminating long lead times
associated with custom oscillators.
®
CLK–
CLK+
Si530 (LVDS/LVPECL/CML)
OE
NC
GND
1
2
3
6
5
4
V
DD
Functional Block Diagram
V
DD
CLK– CLK+
NC
CLK
Si530 (CMOS)
Fixed
Frequency
XO
Any-rate
10–1400 MHz
DSPLL
®
Clock
Synthesis
OE
NC
GND
1
2
3
6
5
4
V
DD
CLK–
CLK+
Si531 (LVDS/LVPECL/CML)
OE
GND
Rev. 1.1 6/07
Copyright © 2007 by Silicon Laboratories
Si530/531
Development of a new type of universal microcomputer protection device for large high-voltage transformers
[b]Development of a new type of universal microcomputer protection device for large high-voltage transformers[/b]...
呱呱 DSP and ARM Processors
PCB board edge distance
I would like to ask, what is the allowable spacing between the edge of the PCB and the [color=#ff0000][b]hole[/b][/color] of the PAD? It will not cause the board to break or crack when drilling. At pr...
bluefox0919 PCB Design
Very low ripple peak-to-peak 1 mV power supply design
I received a design task, requiring a 24V/2A, 12V/2A combined power supply, 1 millivolt ripple peak-to-peak, and a cost of less than 10,000. I wonder which expert can meet such harsh conditions? Linea...
qxvop Power technology
【Altera SoC Experience Tour】High-speed Data Acquisition and Data Transmission (1)
[i=s]This post was last edited by chenzhufly on 2015-4-19 02:03[/i] [align=center][size=3][b]Author: chenzhufly QQ: 36886052[/b][/size][/align][align=left][size=3][b]1. Hardware environment[/b][/size]...
chenzhufly FPGA/CPLD
Basic knowledge of high-speed PCB design
WEEE regulations will be implemented as scheduled, which means that from July 1, 2006, all electronic products sold to the European Union must be lead-free. There are manufacturers who have successful...
clj2004000 PCB Design
How to select DSP and HPIC through PCI2040 in XP
How can I select DSP and HPIC HPIA HPID through PCI2040? Which PCI register should be operated to achieve these goals? I didn't see a clear explanation on the Internet. The document said that PCI_AD14...
skyoflyn Embedded System

EEWorld
subscription
account

EEWorld
service
account

Automotive
development
circle

Robot
development
community

Index Files: 616  2070  1490  2085  406  13  42  30  9  35 
Datasheet   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Room 1530, 15th Floor, Building B, No. 18 Zhongguancun Street, Haidian District, Beijing Telephone: (010) 82350740 Postal Code: 100190
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved 京ICP证060456号 京ICP备10001474号-1 电信业务审批[2006]字第258号函 京公网安备 11010802033920号