530DC895M000DG datasheet, PDF - EEWORLD Datasheet

Datasheet> All Categories > Passive components> oscillator> 530DC895M000DG

530DC895M000DG: DescriptionCMOS/TTL Output Clock Oscillator, 895MHz Nom, ROHS COMPLIANT, SMD, 6 PIN; CategoryPassive components oscillator; File Size215KB，12 Pages; ManufacturerSilicon Laboratories Inc; Environmental Compliance

Download Datasheet Parametric View All

530DC895M000DG Overview

CMOS/TTL Output Clock Oscillator, 895MHz Nom, ROHS COMPLIANT, SMD, 6 PIN

530DC895M000DG Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	Silicon Laboratories Inc
Reach Compliance Code	unknown
Other features	TRAY
maximum descent time	0.35 ns
Frequency Adjustment - Mechanical	NO
frequency stability	7%
JESD-609 code	e4
Manufacturer's serial number	530
Installation features	SURFACE MOUNT
Nominal operating frequency	895 MHz
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Oscillator type	CMOS/TTL
physical size	7.0mm x 5.0mm x 1.85mm
longest rise time	0.35 ns
Maximum supply voltage	3.63 V
Minimum supply voltage	2.97 V
Nominal supply voltage	3.3 V
surface mount	YES
maximum symmetry	55/45 %
Terminal surface	Nickel/Gold (Ni/Au)

Preview

Download Datasheet

View All

S i 5 3 0 / 5 31

EVISION

R Y S TA L

S C I L L A T O R

(XO)

(10 M H

Z T O

1.4 G H

)

Features

Available with any-rate output

frequencies from 10 MHz to 945 MHz

and select frequencies to 1.4 GHz

3rd generation DSPLL

with superior

jitter performance

3x better frequency stability than

SAW-based oscillators

Internal fixed crystal frequency

ensures high reliability and low

aging

Available CMOS, LVPECL,

LVDS, and CML outputs

3.3, 2.5, and 1.8 V supply options

Industry-standard 5 x 7 mm

package and pinout

Pb-free/RoHS-compliant

Si5602

Ordering Information:

See page 7.

Applications

SONET/SDH

Networking

SD/HD video

Test and measurement

Clock and data recovery

FPGA/ASIC clock generation

Pin Assignments:

See page 6.

(Top View)

GND

Description

The Si530/531 XO utilizes Silicon Laboratories’ advanced DSPLL circuitry

to provide a low jitter clock at high frequencies. The Si530/531 is available

with any-rate output frequency from 10 to 945 MHz and select frequencies to

1400 MHz. Unlike a traditional XO, where a different crystal is required for

each output frequency, the Si530/531 uses one fixed crystal to provide a

wide range of output frequencies. This IC based approach allows the crystal

resonator to provide exceptional frequency stability and reliability. In addition,

DSPLL clock synthesis provides superior supply noise rejection, simplifying

the task of generating low jitter clocks in noisy environments typically found in

communication systems. The Si530/531 IC based XO is factory configurable

for a wide variety of user specifications including frequency, supply voltage,

output format, and temperature stability. Specific configurations are factory

programmed at time of shipment, thereby eliminating long lead times

associated with custom oscillators.

CLK–

CLK+

Si530 (LVDS/LVPECL/CML)

GND

Functional Block Diagram

CLK– CLK+

CLK

Si530 (CMOS)

Fixed

Frequency

Any-rate

10–1400 MHz

DSPLL

Clock

Synthesis

GND

CLK–

CLK+

Si531 (LVDS/LVPECL/CML)

GND

Rev. 1.1 6/07

Si530/531

Recommended Resources

Free-running multivibrator using op amp

Use NE555 to make automatic door-controlled lights at night

Delay pulse generator circuit diagram

Protected current expansion circuit diagram

Telephone dialing coding circuit

msp430g2553+nrf24l01 program: I wrote and modified a program to use msp430g2553 to control nrf24l01. The following is the program of the receiving end. It has been tested and can be used. You can refer to it if you need it. #inclu...; hjl240 Microcontroller MCU

How to determine the sample-hold time of msp430ADC?: I have found the formulas for ADC's sample-hold time and conversion time. Sample-hold time = 4×N×ADC12CLK. Conversion time = 13×(ADC12CLK/Fadc12clk). My question now is how to determine the values of ...; adam136 Microcontroller MCU

STM8S207PD7 does not enter interrupt: When I used STM8S207, I found that PD6 could enter interrupt normally, but PD7 could not. The settings were as follows:GPIO_Init(GPIOD, GPIO_PIN_7, GPIO_MODE_IN_PU_IT);I thought that the option byte n...; amountain stm32/stm8

Emerson EV1000 inverter and serial port communication problem: The manual of the EV1000 inverter I use was filed on 2008-08-05. Among its communication protocols - networking modes - single host and single slave, there is a method for the host PC to connect to th...; 等待巴蒂 Embedded System

I'm begging for the topic of Altera Asia Innovation Competition!: I am going to participate in the Altera Asia Innovation Contest soon. Can you recommend a topic for me? It's about SOPC FPGA. The board is Alterra DE1/2. I'm begging for help! Thanks, everyone. This i...; xnmilo Embedded System

Trial Notes of Zhongke Bluexun AB32VG1 RISC-V Development Board: [i=s]This post was last edited by Hot Ximixiu on 2021-8-16 10:31[/i]Trial Notes of Zhongke Bluexun AB32VG1 RISC-V Development Board (Part 1)...; 火辣西米秀 Domestic Chip Exchange

Shortcut: A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF AG AH AI AJ AK AL AM AN AO AP AQ AR AS AT AU AV AW AX AY AZ B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE BF BG BH BI BJ BK BL BM BN BO BP BQ BR BS BT BU BV BW BX BY BZ C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF CG CH CI CJ CK CL CM CN CO CP CQ CR CS CT CU CV CW CX CY CZ D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF DG DH DI DJ DK DL DM DN DO DP DQ DR DS DT DU DV DW DX DZ

Popular Components