531AB1381M00DG datasheet, PDF - EEWORLD Datasheet

Datasheet> All Categories > Passive components> oscillator> 531AB1381M00DG

531AB1381M00DG: DescriptionLVPECL Output Clock Oscillator, 1381MHz Nom, ROHS COMPLIANT, SMD, 6 PIN; CategoryPassive components oscillator; File Size215KB，12 Pages; ManufacturerSilicon Laboratories Inc; Environmental Compliance

Download Datasheet Parametric View All

531AB1381M00DG Overview

LVPECL Output Clock Oscillator, 1381MHz Nom, ROHS COMPLIANT, SMD, 6 PIN

531AB1381M00DG Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	Silicon Laboratories Inc
Reach Compliance Code	unknown
Other features	TRAY
maximum descent time	0.35 ns
Frequency Adjustment - Mechanical	NO
frequency stability	20%
JESD-609 code	e4
Manufacturer's serial number	531
Installation features	SURFACE MOUNT
Nominal operating frequency	1381 MHz
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Oscillator type	LVPECL
physical size	7.0mm x 5.0mm x 1.85mm
longest rise time	0.35 ns
Maximum supply voltage	3.63 V
Minimum supply voltage	2.97 V
Nominal supply voltage	3.3 V
surface mount	YES
maximum symmetry	55/45 %
Terminal surface	Nickel/Gold (Ni/Au)

Preview

Download Datasheet

View All

S i 5 3 0 / 5 31

EVISION

R Y S TA L

S C I L L A T O R

(XO)

(10 M H

Z T O

1.4 G H

)

Features

Available with any-rate output

frequencies from 10 MHz to 945 MHz

and select frequencies to 1.4 GHz

3rd generation DSPLL

with superior

jitter performance

3x better frequency stability than

SAW-based oscillators

Internal fixed crystal frequency

ensures high reliability and low

aging

Available CMOS, LVPECL,

LVDS, and CML outputs

3.3, 2.5, and 1.8 V supply options

Industry-standard 5 x 7 mm

package and pinout

Pb-free/RoHS-compliant

Si5602

Ordering Information:

See page 7.

Applications

SONET/SDH

Networking

SD/HD video

Test and measurement

Clock and data recovery

FPGA/ASIC clock generation

Pin Assignments:

See page 6.

(Top View)

GND

Description

The Si530/531 XO utilizes Silicon Laboratories’ advanced DSPLL circuitry

to provide a low jitter clock at high frequencies. The Si530/531 is available

with any-rate output frequency from 10 to 945 MHz and select frequencies to

1400 MHz. Unlike a traditional XO, where a different crystal is required for

each output frequency, the Si530/531 uses one fixed crystal to provide a

wide range of output frequencies. This IC based approach allows the crystal

resonator to provide exceptional frequency stability and reliability. In addition,

DSPLL clock synthesis provides superior supply noise rejection, simplifying

the task of generating low jitter clocks in noisy environments typically found in

communication systems. The Si530/531 IC based XO is factory configurable

for a wide variety of user specifications including frequency, supply voltage,

output format, and temperature stability. Specific configurations are factory

programmed at time of shipment, thereby eliminating long lead times

associated with custom oscillators.

CLK–

CLK+

Si530 (LVDS/LVPECL/CML)

GND

Functional Block Diagram

CLK– CLK+

CLK

Si530 (CMOS)

Fixed

Frequency

Any-rate

10–1400 MHz

DSPLL

Clock

Synthesis

GND

CLK–

CLK+

Si531 (LVDS/LVPECL/CML)

GND

Rev. 1.1 6/07

Si530/531

Recommended Resources

5V 5A with IC switcher circuit

Industrial product promotion and shopping guide DC power supply circuit

Making LM1875 DC negative feedback BTL power amplifier circuit

Magnetic automatic switch circuit

Interface method of high-precision AD conversion circuit ICL7135 and 8031

Low voltage transformer short circuit protection

Regarding the impact of signal output on the circuit!: I have a strange problem. If I assign a signal in the circuit to an output pin, the logic of the whole circuit is wrong. (If it is not output, the logic is correct when observed through other pins.) H...; eeleader FPGA/CPLD

Get a bottle of Gumianchun.: Get a bottle of Gumianchun....; alfwoo Embedded System

[Launchpad Experience] MSP430 LaunchPad IO External Interrupt (Continuous Mode): #includeint main( void ) {// Stop watchdog timer to prevent time out resetWDTCTL = WDTPW + WDTHOLD;P1DIR |= 0x01;TACCTL0 = CCIE;//Enable the interrupt generated by the CCIFG flagTACCR0 = 50000; (After...; tiankai001 Microcontroller MCU

【Transfer】Design of high-performance, multi-channel, simultaneous sampling ADC in data acquisition system (DAS): [b]Introduction[/b][color=#59595c][font=Arial, Helvetica, sans-serif][size=13px]Many advanced industrial applications require the use of high-performance, multichannel, simultaneous sampling ADCs, suc...; wstt PCB Design

When transmitting data via a modem over a telephone line, there is a delay. What is the reason?: The company uses a strapdown modem to transmit data, the terminal uses a 33600md, and the company headquarters uses a strapdown rack modem. The terminal modem automatically dials and establishes a con...; csaner Embedded System

Debugging access to DSP memory using OCSUnk embedded object: [size=4]Using MATLAB's object-oriented programming technology and CCSLink technology, you can create embedded objects for all C symbols in the target program and operate the C symbols through objects....; fish001 DSP and ARM Processors

Shortcut: A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF AG AH AI AJ AK AL AM AN AO AP AQ AR AS AT AU AV AW AX AY AZ B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE BF BG BH BI BJ BK BL BM BN BO BP BQ BR BS BT BU BV BW BX BY BZ C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF CG CH CI CJ CK CL CM CN CO CP CQ CR CS CT CU CV CW CX CY CZ D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF DG DH DI DJ DK DL DM DN DO DP DQ DR DS DT DU DV DW DX DZ

Popular Components