530MB492M000BG datasheet, PDF - EEWORLD Datasheet

Datasheet> All Categories > Passive components> oscillator> 530MB492M000BG

530MB492M000BG: DescriptionLVPECL Output Clock Oscillator, 492MHz Nom, ROHS COMPLIANT, SMD, 6 PIN; CategoryPassive components oscillator; File Size268KB，15 Pages; ManufacturerSilicon Laboratories Inc; Environmental Compliance

Download Datasheet Parametric View All

530MB492M000BG Overview

LVPECL Output Clock Oscillator, 492MHz Nom, ROHS COMPLIANT, SMD, 6 PIN

530MB492M000BG Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	Silicon Laboratories Inc
Reach Compliance Code	unknown
Other features	TRAY
maximum descent time	0.35 ns
Frequency Adjustment - Mechanical	NO
frequency stability	20%
JESD-609 code	e4
Manufacturer's serial number	530
Installation features	SURFACE MOUNT
Nominal operating frequency	492 MHz
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Oscillator type	LVPECL
physical size	7.0mm x 5.0mm x 1.85mm
longest rise time	0.35 ns
Maximum supply voltage	3.63 V
Minimum supply voltage	2.97 V
Nominal supply voltage	3.3 V
surface mount	YES
maximum symmetry	55/45 %
Terminal surface	Nickel/Gold (Ni/Au)

Preview

Download Datasheet

View All

S i 5 3 0 / 5 31

R Y S TA L

S C I L L A T O R

(XO)

(10 M H

Z T O

1.4 G H

)

Features

Available with any-rate output

frequencies from 10 MHz to 945 MHz

and select frequencies to 1.4 GHz

3rd generation DSPLL

with superior

jitter performance

3x better frequency stability than

SAW-based oscillators

Internal fixed crystal frequency

ensures high reliability and low

aging

Available CMOS, LVPECL,

LVDS, and CML outputs

3.3, 2.5, and 1.8 V supply options

Industry-standard 5 x 7 mm

package and pinout

Pb-free/RoHS-compliant

Si5602

Ordering Information:

See page 7.

Applications

SONET/SDH

Networking

SD/HD video

Test and measurement

Clock and data recovery

FPGA/ASIC clock generation

Pin Assignments:

See page 6.

(Top View)

GND

Description

The Si530/531 XO utilizes Silicon Laboratories’ advanced DSPLL circuitry

to provide a low jitter clock at high frequencies. The Si530/531 is available

with any-rate output frequency from 10 to 945 MHz and select frequencies to

1400 MHz. Unlike a traditional XO, where a different crystal is required for

each output frequency, the Si530/531 uses one fixed crystal to provide a

wide range of output frequencies. This IC based approach allows the crystal

resonator to provide exceptional frequency stability and reliability. In addition,

DSPLL clock synthesis provides superior supply noise rejection, simplifying

the task of generating low jitter clocks in noisy environments typically found in

communication systems. The Si530/531 IC based XO is factory configurable

for a wide variety of user specifications including frequency, supply voltage,

output format, and temperature stability. Specific configurations are factory

programmed at time of shipment, thereby eliminating long lead times

associated with custom oscillators.

CLK–

CLK+

Si530 (LVDS/LVPECL/CML)

GND

Functional Block Diagram

CLK– CLK+

CLK

Si530 (CMOS)

Fixed

Frequency

Any-rate

10–1400 MHz

DSPLL

Clock

Synthesis

GND

CLK–

CLK+

Si531 (LVDS/LVPECL/CML)

GND

Rev. 1.0 7/06

Si530/531

Recommended Resources

TA7230P power amplifier circuit diagram

Single touch light switch circuit (5)

Huahong CDR30LB-CDR150WB electric water heater circuit diagram

Self-sensing feedback ten-channel encoder

555 temperature/frequency conversion circuit (2)

Pulse source with preset number of pulses

The wiring method of the equipment is really troublesome...: I recently visited several construction sites, and the most common question asked by the on-site staff was how to connect various devices. Take an electric valve for example, each manufacturer has a d...; fish001 Industrial Control Electronics

Typical circuit diagram of switching power supply + ripple and noise test method of switching power supply: Ripple and noise test methods for switching power supplies...; 晴天余霞 51mcu

MCP3201 Device Study: MCP3201 is a 2.7V, 12-bit A/D converter with SPI serial interface. It has the following features:* 12-bit resolution * On-chip sample and hold circuit* SPI serial interface* Single power supply 2.7~5....; eeleader FPGA/CPLD

Read BMP280 via IIC using 51 MCU: I would like to ask if anyone has used 51 to read the atmospheric pressure data of BMP280? The examples on the Internet are all for 32 and Arduino, and I have not succeeded in transplanting it myself....; 2413529458 51mcu

Geek forced uninstall tool GeekUninstaller (1.4.0.88) green single file version: [b][size=5]Geek Uninstaller (1.4.0.88) Green Single File Version[/size][/b] GeekUninstaller is a free professional single file green uninstall tool tailored for "geeks". It has many outstanding featur...; 葵花宝典666 Download Centre

Basys3 Oscilloscope Experiment Design Based on FPGA Vivado 17.2: Based on FPGA vivado 17.2 Basys3 oscilloscope experiment design attachment:[b][color=#5E7384]This content is originally created by EEWORLD forum user [size=3]大辉哥0614[/size]. If you need to reprint or ...; 大辉哥0614 FPGA/CPLD

Shortcut: A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF AG AH AI AJ AK AL AM AN AO AP AQ AR AS AT AU AV AW AX AY AZ B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE BF BG BH BI BJ BK BL BM BN BO BP BQ BR BS BT BU BV BW BX BY BZ C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF CG CH CI CJ CK CL CM CN CO CP CQ CR CS CT CU CV CW CX CY CZ D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF DG DH DI DJ DK DL DM DN DO DP DQ DR DS DT DU DV DW DX DZ

Popular Components