554AF000208BG datasheet, PDF - EEWORLD Datasheet

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554AF000208BG: DescriptionLVPECL Output Clock Oscillator, 250MHz Nom, ROHS COMPLIANT, SMD, 8 PIN; CategoryPassive components oscillator; File Size3MB，115 Pages; ManufacturerSilicon Laboratories Inc; Environmental Compliance

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554AF000208BG Overview

LVPECL Output Clock Oscillator, 250MHz Nom, ROHS COMPLIANT, SMD, 8 PIN

554AF000208BG Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	Silicon Laboratories Inc
Reach Compliance Code	unknown
Other features	IT CAN ALSO OPERATE AT 248.83200 MHZ, 212.50000 MHZ AND 200.00000 MHZ
Maximum control voltage	3.3 V
Minimum control voltage
maximum descent time	0.35 ns
Frequency Adjustment - Mechanical	NO
Frequency offset/pull rate	100 ppm
frequency stability	50%
JESD-609 code	e4
Manufacturer's serial number	554
Installation features	SURFACE MOUNT
Nominal operating frequency	250 MHz
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Oscillator type	LVPECL
physical size	177.8mm x 127.0mm x 41.91mm
longest rise time	0.35 ns
Maximum supply voltage	3.63 V
Minimum supply voltage	2.97 V
Nominal supply voltage	3.3 V
surface mount	YES
maximum symmetry	55/45 %
Terminal surface	Nickel/Gold (Ni/Au)

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Si554

U A D

R E Q U E N C Y

VCXO (10 MH

Z T O

1.4 GH

)

Features

Available with any-rate output

frequencies from 10–945 MHz and

select frequencies to 1.4 GHz

Four selectable output frequencies

3rd generation DSPLL

with superior

jitter performance

3x better frequency stability than

SAW-based oscillators

Internal fixed crystal frequency

ensures high reliability and low

aging

Available CMOS, LVPECL, LVDS

& CML outputs

3.3, 2.5, and 1.8 V supply options

Industry-standard 5 x 7 mm

package and pinout

Pb-free/RoHS-compliant

Si5602

Applications

SONET/SDH

xDSL

10 GbE LAN / WAN

Low jitter clock generation

Optical Modules

Clock and data recovery

Ordering Information:

See page 7.

Description

The Si554 quad frequency VCXO utilizes Silicon Laboratories advanced

DSPLL

circuitry to provide a very low jitter clock for all output frequencies.

The Si554 is available with any-rate output frequency from 10 to 945 MHz

and select frequencies to 1400 MHz. Unlike traditional VCXOs where a

different crystal is required for each output frequency, the Si554 uses one

fixed crystal frequency to provide a wide range of output frequencies. This

IC based approach allows the crystal resonator to provide exceptional

frequency stability and reliability. In addition, DSPLL clock synthesis

provides superior supply noise rejection, simplifying the task of generating

low jitter clocks in noisy environments typically found in communication

systems. The Si554 IC-based VCXO is factory configurable for a wide

variety of user specifications including frequency, supply voltage, output

format, tuning slope, and temperature stability. Specific configurations are

factory programmed at time of shipment, thereby eliminating long lead times

associated with custom oscillators.

Pin Assignments:

See page 6.

(Top View)

FS[1]

FS[0]

GND

CLK–

CLK+

Functional Block Diagram

CLK- CLK+

FS1

Fixed

Frequency XO

Any-rate

10–1400 MHz

DSPLL

Clock Synthesis

FS0

ADC

GND

Rev. 0.5 7/06

Si554

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