531AB1272M00BG datasheet, PDF - EEWORLD Datasheet

Datasheet> All Categories > Passive components> oscillator> 531AB1272M00BG

531AB1272M00BG: DescriptionLVPECL Output Clock Oscillator, 1272MHz Nom, ROHS COMPLIANT, SMD, 6 PIN; CategoryPassive components oscillator; File Size268KB，15 Pages; ManufacturerSilicon Laboratories Inc; Environmental Compliance

Download Datasheet Parametric View All

531AB1272M00BG Overview

LVPECL Output Clock Oscillator, 1272MHz Nom, ROHS COMPLIANT, SMD, 6 PIN

531AB1272M00BG Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	Silicon Laboratories Inc
Reach Compliance Code	unknown
Other features	TRAY
maximum descent time	0.35 ns
Frequency Adjustment - Mechanical	NO
frequency stability	20%
JESD-609 code	e4
Manufacturer's serial number	531
Installation features	SURFACE MOUNT
Nominal operating frequency	1272 MHz
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Oscillator type	LVPECL
physical size	7.0mm x 5.0mm x 1.85mm
longest rise time	0.35 ns
Maximum supply voltage	3.63 V
Minimum supply voltage	2.97 V
Nominal supply voltage	3.3 V
surface mount	YES
maximum symmetry	55/45 %
Terminal surface	Nickel/Gold (Ni/Au)

Preview

Download Datasheet

View All

S i 5 3 0 / 5 31

R Y S TA L

S C I L L A T O R

(XO)

(10 M H

Z T O

1.4 G H

)

Features

Available with any-rate output

frequencies from 10 MHz to 945 MHz

and select frequencies to 1.4 GHz

3rd generation DSPLL

with superior

jitter performance

3x better frequency stability than

SAW-based oscillators

Internal fixed crystal frequency

ensures high reliability and low

aging

Available CMOS, LVPECL,

LVDS, and CML outputs

3.3, 2.5, and 1.8 V supply options

Industry-standard 5 x 7 mm

package and pinout

Pb-free/RoHS-compliant

Si5602

Ordering Information:

See page 7.

Applications

SONET/SDH

Networking

SD/HD video

Test and measurement

Clock and data recovery

FPGA/ASIC clock generation

Pin Assignments:

See page 6.

(Top View)

GND

Description

The Si530/531 XO utilizes Silicon Laboratories’ advanced DSPLL circuitry

to provide a low jitter clock at high frequencies. The Si530/531 is available

with any-rate output frequency from 10 to 945 MHz and select frequencies to

1400 MHz. Unlike a traditional XO, where a different crystal is required for

each output frequency, the Si530/531 uses one fixed crystal to provide a

wide range of output frequencies. This IC based approach allows the crystal

resonator to provide exceptional frequency stability and reliability. In addition,

DSPLL clock synthesis provides superior supply noise rejection, simplifying

the task of generating low jitter clocks in noisy environments typically found in

communication systems. The Si530/531 IC based XO is factory configurable

for a wide variety of user specifications including frequency, supply voltage,

output format, and temperature stability. Specific configurations are factory

programmed at time of shipment, thereby eliminating long lead times

associated with custom oscillators.

CLK–

CLK+

Si530 (LVDS/LVPECL/CML)

GND

Functional Block Diagram

CLK– CLK+

CLK

Si530 (CMOS)

Fixed

Frequency

Any-rate

10–1400 MHz

DSPLL

Clock

Synthesis

GND

CLK–

CLK+

Si531 (LVDS/LVPECL/CML)

GND

Rev. 1.0 7/06

Si530/531

Recommended Resources

The service life of some components of the switching power supply

CJ-12 type excitation regulating machine circuit

Electronic potential circuit composed of digital circuits

5V, 0.5A step-down converter circuit

Common inverter schematics on the market (12VDC to 220VAC 150W)

SAMSUNG CME20G microwave oven circuit

Verilog HDL exercises and Verilog basics suitable for newcomers to Verilog.rar: Verilog HDL exercises and Verilog basics are suitable for Verilog beginners135 classic design examples of Verilog...; 493025560 FPGA/CPLD

Comparison between Altium Designer 14 and 10: [p=22, null, left][color=#4d4b4b][font=宋体, Arial, Helvetica, sans-serif]Author: Zhu Changjiang[/font][/color][/p][p=22, null, left][color=#4d4b4b][font=宋体, Arial, Helvetica, sans-serif] Altium Designe...; qwqwqw2088 PCB Design

Discussion on EMI rules for high-speed PCB design (Part 2): [size=2]Rule 5: Routing direction rules for high-speed PCB design The routing between two adjacent layers must follow the principle of vertical routing, otherwise it will cause crosstalk between lines...; 心仪 PCB Design

There is no LM5117 in the Multisim14.0 simulation library: Where can I download the schematic library of LM5117?...; 激射电火花 Electronics Design Contest

LCD 1602 display source code: LCD 1602 display source code #includereg52.h#define uint unsigned int#define uchar unsigned charsbit en=P2^0;sbit rs=P2^1;uchar code table[]="I LOVE YOU";uchar code table1[]="FOREVER MAMA!";uchar num;...; guoyuanqiang MCU

Program Jump: void send (uchar n) {SBUF=n;while(!IF) ;IF=0; }void main() {SP=0x30;init_cpu(); //This function sets up serial communicationwhile(1){send(0x01);P1=0x01;send(0x02);P1=0x02;send(0x03);P1=0x03;send(0x04)...; scorpius 51mcu

Shortcut: A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF AG AH AI AJ AK AL AM AN AO AP AQ AR AS AT AU AV AW AX AY AZ B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE BF BG BH BI BJ BK BL BM BN BO BP BQ BR BS BT BU BV BW BX BY BZ C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF CG CH CI CJ CK CL CM CN CO CP CQ CR CS CT CU CV CW CX CY CZ D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF DG DH DI DJ DK DL DM DN DO DP DQ DR DS DT DU DV DW DX DZ

Popular Components