EEWORLDEEWORLDEEWORLD

Part Number

Search

531MA314M000BG

Description
LVPECL Output Clock Oscillator, 314MHz Nom, ROHS COMPLIANT, SMD, 6 PIN
CategoryPassive components    oscillator   
File Size268KB,15 Pages
ManufacturerSilicon Laboratories Inc
Environmental Compliance  
Download Datasheet Parametric View All

531MA314M000BG Overview

LVPECL Output Clock Oscillator, 314MHz Nom, ROHS COMPLIANT, SMD, 6 PIN

531MA314M000BG Parametric

Parameter NameAttribute value
Is it lead-free?Lead free
Is it Rohs certified?conform to
MakerSilicon Laboratories Inc
Reach Compliance Codeunknown
Other featuresTRAY
maximum descent time0.35 ns
Frequency Adjustment - MechanicalNO
frequency stability50%
JESD-609 codee4
Manufacturer's serial number531
Installation featuresSURFACE MOUNT
Nominal operating frequency314 MHz
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
Oscillator typeLVPECL
physical size7.0mm x 5.0mm x 1.85mm
longest rise time0.35 ns
Maximum supply voltage3.63 V
Minimum supply voltage2.97 V
Nominal supply voltage3.3 V
surface mountYES
maximum symmetry55/45 %
Terminal surfaceNickel/Gold (Ni/Au)
S i 5 3 0 / 5 31
C
R Y S TA L
O
S C I L L A T O R
(XO)
(10 M H
Z T O
1.4 G H
Z
)
Features
Available with any-rate output
frequencies from 10 MHz to 945 MHz
and select frequencies to 1.4 GHz
3rd generation DSPLL
®
with superior
jitter performance
3x better frequency stability than
SAW-based oscillators
Internal fixed crystal frequency
ensures high reliability and low
aging
Available CMOS, LVPECL,
LVDS, and CML outputs
3.3, 2.5, and 1.8 V supply options
Industry-standard 5 x 7 mm
package and pinout
Pb-free/RoHS-compliant
Si5602
Ordering Information:
See page 7.
Applications
SONET/SDH
Networking
SD/HD video
Test and measurement
Clock and data recovery
FPGA/ASIC clock generation
Pin Assignments:
See page 6.
(Top View)
NC
OE
GND
1
2
3
6
5
4
V
DD
Description
The Si530/531 XO utilizes Silicon Laboratories’ advanced DSPLL circuitry
to provide a low jitter clock at high frequencies. The Si530/531 is available
with any-rate output frequency from 10 to 945 MHz and select frequencies to
1400 MHz. Unlike a traditional XO, where a different crystal is required for
each output frequency, the Si530/531 uses one fixed crystal to provide a
wide range of output frequencies. This IC based approach allows the crystal
resonator to provide exceptional frequency stability and reliability. In addition,
DSPLL clock synthesis provides superior supply noise rejection, simplifying
the task of generating low jitter clocks in noisy environments typically found in
communication systems. The Si530/531 IC based XO is factory configurable
for a wide variety of user specifications including frequency, supply voltage,
output format, and temperature stability. Specific configurations are factory
programmed at time of shipment, thereby eliminating long lead times
associated with custom oscillators.
®
CLK–
CLK+
Si530 (LVDS/LVPECL/CML)
OE
NC
GND
1
2
3
6
5
4
V
DD
Functional Block Diagram
V
DD
CLK– CLK+
NC
CLK
Si530 (CMOS)
Fixed
Frequency
XO
Any-rate
10–1400 MHz
DSPLL
®
Clock
Synthesis
OE
NC
GND
1
2
3
6
5
4
V
DD
CLK–
CLK+
Si531 (LVDS/LVPECL/CML)
OE
GND
Rev. 1.0 7/06
Copyright © 2006 by Silicon Laboratories
Si530/531
Can SD cards be written in blocks smaller than 512 bytes at a time?
I can now write blocks of 512, but not smaller ones. For example, I can't write 16 bytes, but I can read 16 bytes without any problem.The SD card manual says that the SD card can set the read and writ...
bogedahan12 stm32/stm8
Ask Mr. Xia
Teacher Xia: Hello, first of all, thank you very much for answering our questions. I really appreciate it. There are too few people doing good deeds nowadays. It is a bit unrealistic for teachers to a...
swgwy1985 FPGA/CPLD
Implementing HIVE registry on SD card, screen goes blank
1,02400" (0x0000400) 1,02400 (0x0000400) 0,000000 (0x00000400) 1,02400 (0x00000400) 0,000000 (0x00000400) 1,02400 (0x00000400) 0,000000 (0x000000400) 0,000000 (0x000000400) 1,02400 (0x00000400) 0,0000...
wanghai8521 Embedded System
I recently helped someone tune LF2406A, and I have some knowledge about TI's low-end Flash DSP. Welcome to exchange ideas.
The most impressive thing is that Flash is mapped to PM, with only a small amount of SRAM on the chip; this makes the Load Program method completely ineffective during program debugging, and always pr...
philoman DSP and ARM Processors
EEWORLD University Hall----FPGA Video Transmission
FPGA video transmission : https://training.eeworld.com.cn/course/2133In this example, two VEEK-MT FPGA development platforms are used to transmit video to each other through analog-to-digital converte...
chenyy FPGA/CPLD
MaixSense R329 development board Tina system test
This time, we will conduct a power-on experiment on the development board. First, we will burn the Tina system. The Tina system is a system developed by Allwinner for the modified OpenWRT1404 . It is ...
zzx1997 Domestic Chip Exchange

EEWorld
subscription
account

EEWorld
service
account

Automotive
development
circle

Robot
development
community

Index Files: 437  727  681  2774  543  9  15  14  56  11 
Datasheet   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Room 1530, 15th Floor, Building B, No. 18 Zhongguancun Street, Haidian District, Beijing Telephone: (010) 82350740 Postal Code: 100190
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved 京ICP证060456号 京ICP备10001474号-1 电信业务审批[2006]字第258号函 京公网安备 11010802033920号