EEWORLDEEWORLDEEWORLD

Part Number

Search

5G64B-200M-FREQ

Description
HCMOS/TTL Output Clock Oscillator, 1MHz Min, 50MHz Max, ROHS COMPLIANT, MINIATURE, SMD, 6 PIN
CategoryPassive components    oscillator   
File Size346KB,1 Pages
ManufacturerEuroquartz
Websitehttp://www.euroquartz.co.uk/
Environmental Compliance  
Download Datasheet Parametric View All

5G64B-200M-FREQ Overview

HCMOS/TTL Output Clock Oscillator, 1MHz Min, 50MHz Max, ROHS COMPLIANT, MINIATURE, SMD, 6 PIN

5G64B-200M-FREQ Parametric

Parameter NameAttribute value
Is it lead-free?Lead free
Is it Rohs certified?conform to
MakerEuroquartz
Reach Compliance Codecompliant
Maximum control voltage4.5 V
Minimum control voltage0.5 V
maximum descent time0.7 ns
Frequency Adjustment - MechanicalNO
Frequency offset/pull rate200 ppm
frequency stability50%
linearity10%
Installation featuresSURFACE MOUNT
Maximum operating frequency50 MHz
Minimum operating frequency1 MHz
Maximum operating temperature70 °C
Minimum operating temperature
Oscillator typeHCMOS/TTL
Output load2 TTL, 15 pF
physical size11.4mm x 9.6mm x 4.7mm
longest rise time0.7 ns
Maximum supply voltage5.25 V
Minimum supply voltage4.75 V
Nominal supply voltage5 V
surface mountYES
maximum symmetry55/45 %
EURO
QUARTZ
Frequency range 0.625MHz to 50.0MHz
CMOS/TTL Output
Supply Voltage 5.0 V or 3.3 VDC
Integrated Phase Jitter 1ps typical
DESCRIPTION
OUTLINE & DIMENSIONS
G64 VCXOs, are packaged in a miniature 11.4mm x 9.6mm x 4.7mm
6 pad SMD package. Typical phase jitter for G series VCXOs is <1ps,
output CMOS/TTL. G series VCXOs use fundamental mode crystal
osccillators. Applications include phase lock loop, SONET/ATM, set-
top boxes, MPEG , audio/video modulation, video game consoles and
HDTV.
SPECIFICATION
Frequency Range
Vdd = +3.3VDC:
0.625MHz to 50.0MHz
Vdd = +5.0VDC:
1.0MHz to 50.0MHz
Supply Voltage:
+3.3 VDC ±5% or +5.0VDC±5%
Output Logic:
TTL/HCMOS
Integrated Phase Jitter:
1.0ps maximum 12kHz to 20MHz
Period Jitter RMS:
2.0ps typical
Period Jitter Peak to Peak:
14ps maximum
Phase Noise:
See table below
Initial Frequency Accuracy
Tune to the nominal frequency with:
+3.3VDC:
Vc= 1.65V ±0.2V
+5.0 VDC:
Vc= 2.5V ±0.2V
Output Voltage HIGH (1):
90% Vdd minimum
Output Voltage LOW (0):
10% Vdd maximum
Control Voltage Centre
+3.3VDC:
1.65V
+5.0VDC:
2.5V
Control Voltage Range
+3.3VDC:
0.3V to 3.0V
+5.0VDC:
0.5V to 4.5V
Pulling Range
+3.3VDC
±80ppm to ±120ppm (standard)
+5.0VDC:
±80ppm to ±150ppm
(±200ppm available)
Temperature Stability:
See table
Output Load:
CMOS = 15pF, TTL = 2 gates
Start-up Time:
10ms maximum, 5ms typical
Duty Cycle:
50% ±5% measured at 50% Vdd
Rise/Fall Times:
0.7ns typical (15pF load)
Current Consumption:
10 to 45mA, frequency
dependent
Linearity:
10% maximum, 6% typical
Modulation Bandwidth:
10kHz minimum
Input Impedance:
1 MW minimum
Slope Polarity:
Monotonic and Positive. (An
(Transfer function)
increase of control voltage
always increases output
frequency.)
Storage Temperature:
-50° to +100°C
Ageing:
±5ppm per year maximum
RoHS Status:
Fully compliant
FREQUENCY STABILITY
Stability Code Stability ±ppm Temp. Range
A
25
0°~+70°C
B
50
0°~+70°C
C
100
0°~+70°C
D
25
-40°~+85°C
E
50
-40°~+85°C
F
100
-40°~+85°C
If non-standard frequency stability is required
Use ‘I’ followed by stability, i.e. I20 for ±20ppm
G64 CMOS VCXO
11.4 x 9.6 x 4.7mm 6 pad SMD
PHASE NOISE
Offset
10Hz
100Hz
1kHz
10kHz
1MHz
Frequency 27.0MHz
-70dBc/Hz
-105dBc/Hz
-132dBc/Hz
-142dBc/Hz
-150dBc/Hz
PART NUMBERING
Example:
Supply Voltage
3 = +3.3V
5 = +5.0V
Series Designator
G64
Stability over temperature range
(See table)
Pullability in ±ppm
Pullability determinator
N = minimum
M = maximum
T = Typical
Frequency in MHz
3 G64 B-80N-27.000
EUROQUARTZ LIMITED Blacknell Lane CREWKERNE Somerset UK TA18 7HE
Tel: +44 (0)1460 230000 Fax: +44 (0)1460 230001 Email: info@euroquartz.co.uk www.euroquartz.co.uk
USB Blaster Issues (Purchase and Production)
Altera's FPGA/CPLD program download cable can be used to program and debug Altera's FPGA/CPLD and configuration chips through the computer's USB interface. USB-Blaster drives the configuration or prog...
paulhyde FPGA/CPLD
DS1302 clock chip driver
DS1302 clock chip driver...
fighting PCB Design
How to test isolation amplifiers?
I would like to ask all the engineers humbly about the testing principles and methods of isolation amplifiers. What type of ATE is used for mass production testing? Thank you in advance!...
linda_xia Analog electronics
What is the difference between software engineering and embedded system?
I like to work on software, but recently I always hear that embedded systems have more prospects. Since I don’t know much about embedded systems, I hope to get help from experts. . . ....
85868788 Embedded System
How to implement frequency meter using Zigbee (CC2530)?
How to implement a frequency counter using Zigbee (CC2530)? How to write the software and connect the hardware?...
天平舞者 RF/Wirelessly
5# Analysis of Bluetooth routines on STM32WB development board
[i=s] This post was last edited by Beifang on 2019-5-13 12:49 [/i] 1. ST's SDK provides a relatively rich set of examples, but the examples for dual-core use have not been added yet. They should be ad...
北方 RF/Wirelessly

EEWorld
subscription
account

EEWorld
service
account

Automotive
development
circle

Robot
development
community

Index Files: 109  332  1171  1244  203  3  7  24  26  5 
Datasheet   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Room 1530, 15th Floor, Building B, No. 18 Zhongguancun Street, Haidian District, Beijing Telephone: (010) 82350740 Postal Code: 100190
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved 京ICP证060456号 京ICP备10001474号-1 电信业务审批[2006]字第258号函 京公网安备 11010802033920号