PRO-LINX
™
GS7005
Complete Serial Digital Video Receiver
DATA SHEET
FEATURES
• SMPTE 259M-C compliant
• fully integrated 270 Mb/s SDI receiver
• integrated cable equalization (100m Belden 8281 typical)
• low power consumption (750mW typical)
• operates from 0°C to 85°C
• small footprint with minimal external components
• Lock and Carrier Detect output indications
• H timing signal output
• SMPTE descrambler and NRZI decoder may be
disabled for DVB - ASI applications
• ease of design use and adjustment free operation
ORDERING INFORMATION
APPLICATIONS
Limited space, low power SMPTE 259M-C or generic
270Mb/s serial to parallel interfaces; DVB-ASI 270Mb/s
receive interface; broadcast quality uncompressed video
interface for industrial and professional video equipment
such as video editing workstations.
PART NUMBER
GS7005 - CQT
GS7005 - CTT
PACKAGE
52 pin MQFP
52 pin MQFP Tape
TEMPERATURE
0°C to 85°C
0°C to 85°C
DESCRIPTION
The GS7005 is a BiCMOS integrated circuit capable of
operating as a complete 270Mb/s Serial Digital Video
receiver. The GS7005 provides a complete serial digital
video receive solution while consuming only 750mW.
The serial data input accepts SMPTE 259M-C compliant
signals. An on-chip by-passable equalizer typically pro-
vides 100m of co-axial cable equalization. The clock
recovery is performed on chip with minimal external
components. The incoming serial data is decoded using an
NRZI decoder and SMPTE descrambler to provide SMPTE
125M compliant 27Mb/s parallel data outputs and clock.
GS7005
C
1
C
2
LOCK
CD
SIGNAL
LOCK
DETECT
PLL
f/10
PCLK
OUT
H
MUX
TRS
DETECTOR
SDI
SDI
EQUALIZER
SLICER
NRZI
DECODER
DESCRAMBLER
S to P
10
D
OUT[9:0}
EQ
SMPTE
BLOCK DIAGRAM
Revision Date: January 2001
GENNUM CORPORATION P.O. Box 489, Stn. A, Burlington, Ontario, Canada L7R 3Y3
Tel. +1 (905) 632-2996 Fax. +1 (905) 632-5946 E-mail: info@gennum.com
www.gennum.com
Document No. 522 - 14 - 06
ABSOLUTE MAXIMUM RATINGS
PARAMETER
Supply Voltage
Input Voltage Range (any input)
DC Input Current (any one input)
Power Dissipation (V
CC
= 5.25V)
Maximum Die Temperature
Operating Temperature Range
Storage Temperature Range
Lead Temperature (soldering 10s)
VALUE
5.5V
GND < V
IN
< V
CC
10mA
GS7005
1W
125°C
0°C <= T
A
<= 85°C
-65°C <= T
S
<= 150°C
260°C
DC ELECTRICAL CHARACTERISTICS
V
CC
= 5V, T
A
= 25°C, unless otherwise specified.
Serial data rate = 270Mb/s, Parallel Data Rate = 27Mb/s, ƒ
PCLK
= 27MHz
PARAMETER
Positive Supply Voltage
SYMBOL
V
CC
P
I
CC
V
IL
V
IH
V
OL
V
OH
CONDITIONS
Operating
range
V
CC
= 5.25V
V
CC
= 5.25V
V
CC
= 5.25V
V
CC
= 4.75V
V
CC
= 5.25V
V
CC
= 4.75V
MIN
4.75
TYP
5.00
MAX
5.25
UNITS
V
NOTES
TEST LEVEL
6
Power Consumption
Supply Current
Logic Inputs - Low
Logic Inputs - High
Logic Outputs - Low
Logic Outputs - High
TEST LEVELS
-
-
-
2
-
2.4
750
140
-
-
-
-
-
-
0.8
-
0.5
-
mW
mA
V
V
V
V
5
1
6
6
1
1
1. Production test at room temperature and nominal supply voltage with guardbands for supply and temperature ranges.
2. Production test at room temperature and nominal supply voltage with guardbands for supply and temperature ranges using
correlated test.
3. Production test at room temperature and nominal supply voltage.
4. QA sample test.
5. Calculated result based on Level 1,2, or 3.
6. Not tested. Guaranteed by design simulations.
7. Not tested. Based on characterization of nominal parts.
8. Not tested. Based on existing design/characterization data of similar product.
2
GENNUM CORPORATION
522 - 14 - 06
AC ELECTRICAL CHARACTERISTICS
V
CC
= 5V, T
A
= 25°C, unless otherwise specified in ‘conditions’
Serial data rate = 270Mb/s, Parallel Data Rate = 27Mb/s, ƒ
PCLK
= 27MHz
PARAMETER
Parallel Data - Rise/Fall Time
PCLK Rising Edge to D
OUT(N)
Centre
PCLK Rise/Fall Time
Input Return Loss
SYMBOL
t
R/F_DOUT
t
D
t
R/F_PCLKOUT
LOSS
IN
CONDITIONS
C
L
= 20pF
MIN
1.0
-
TYP
-
-
-
17
MAX
6.0
±5
3.0
-
UNITS
ns
ns
ns
dB
NOTE
S
1
2, 3
1
TEST
LEVEL
4, 7
4, 7
4, 7
7
GS7005
C
L
= 20pF
75Ω match
5MHz to 270MHz
0.5
-
Asynchronous Lock Time
Synchronous Lock Time
Input Jitter Tolerance
Output PCLK Jitter
t
LOCK_ASYNC
t
LOCK_SYNC
t
J_SI
t
J_PCLKOUT
Pathological Input
Pseudorandom
Input
Pathological Input
-
-
-
-
-
-
0.35
800
250
10
-
-
ms
µs
U.I.
ps p-p
4
5
6
1
1
7
1
-
-
1000
100
-
-
ps p-p
m
6
7
7
Error Free Cable Length
Pseudorandom
Input
Pathological Input
75
100
-
m
6, 7
1
NOTES
1. Rise/Fall time is defined as the time for the signal to rise from 20% to 80% of the specified p-p value, or to fall from 80% to 20% of the
specified value.
2. Refer also to Figure 10.
3. This is the time difference between the rising edge of PCLK
OUT
and the centre of the bit period.
4. This is the time delay between a valid serial TRS signal on the input to the moment valid data appears on the parallel outputs.
5. This is the time for the PLL to re-lock when video streams are switched during the vertical blanking interval in accordance with SMPTE
RP168-1993. The two streams may be 180° out of phase with respect to one another, but pixel aligned.
6. This pathological pattern is defined in SMPTE RP178-1996, paragraphs 4.1 and 4.3.
7. "Error free" is defined as no single bit errors over a period of 10 minutes, using Belden 8281 Cable and 75Ω connections. The MIN
value is fully tested and the TYP value is based on using the EB7005 Evaluation Board.
TEST LEVELS
1. Production test at room temperature and nominal supply voltage with guardbands for supply and temperature ranges.
2. Production test at room temperature and nominal supply voltage with guardbands for supply and temperature ranges using correlated
test.
3. Production test at room temperature and nominal supply voltage.
4. QA sample test.
5. Calculated result based on Level 1,2, or 3.
6. Not tested. Guaranteed by design simulations.
7. Not tested. Based on characterization of nominal parts.
8. Not tested. Based on existing design/characterization data of similar product.
3
GENNUM CORPORATION
522 - 14 - 06
TEST SETUP
DATA
TEKTRONIX
GigaBERT
1400
TRANSMITTER
DATA
GS9028
CABLE
DRIVER
BELDEN 8281
CABLE
GS7005
EB7005
BOARD
TEKTRONIX
TDS 820
SCOPE
CLOCK
TRIGGER
Fig. 1a Test Setup for Jitter Measurements
TEKTRONIX
VIDEO SlGNAL
GENERATOR
VIDEO STREAM
WITH EDH
BELDEN 8281
CABLE
EB7005
BOARD
EB9021
EDH ERROR
COUNTER
Fig. 1b Test Setup for Error-Free Cable Length
HP 4195A
NETWORK
ANALYSER
BELDEN 8281
CABLE
EB7005
BOARD
Fig. 1c Test Setup for Return Loss Measurements
4
GENNUM CORPORATION
522 - 14 - 06
PIN CONNECTIONS
GND
GND
RSVD1
RSVD1
V
CC3
CD
SMPTE
RSVD0
RSVD0
PCLK
OUT
V
DD
GND
GND
52 51 50 49 48 47 46 45 44 43 42 41 40
1
2
3
4
5
GS7005
6
TOP VIEW
7
8
9
10
11
12
13 14 15 16 17 18 19 20 21 22 23 24 25 26
GND
GND
C
1
C
2
V
CC1
SDI
SDI
V
CC2
RSVD0
GND
EQ
RSVD1
GND
39
38
37
36
35
34
33
32
31
30
29
28
27
GND
RSVD0
RSVD0
RSVD0
RSVD0
RSVD0
RSVD0
RSVD0
RSVD0
RSVD0
RSVD0
H
GND
GND
D
OUT0
D
OUT1
D
OUT2
D
OUT3
D
OUT4
D
OUT5
D
OUT6
D
OUT7
D
OUT8
D
OUT9
LOCK
GND
GS7005
NOTE:
RSVD = Reserved
PIN DESCRIPTIONS
NUMBER
1, 13, 14, 26, 27,
39, 40, 52
2-11, 22, 44, 45
12
15
16, 17
18
19, 20
21
23
24
25, 49, 50
28
29-38
41
42
43
46
SYMBOL
GND
RSVD0
H
GND
C
1
, C
2
V
CC1
SDI, SDI
V
CC2
GND
EQ
RSVD1
LOCK
D
OUT[9:0]
GND
V
DD
PCLK
OUT
SMPTE
TYPE
-
-
O
-
-
-
I
-
-
I
-
O
O
-
-
O
I
Connect to Ground.
Connect to Ground.
H Indication. HIGH after EAV ID and LOW after SAV ID.
Ground for analog blocks of the device.
External 100nF loop filter capacitor connection.
Power supply for analog blocks of the device.
Differential Serial Data Input
Power supply for PECL blocks of the device.
Ground for PECL blocks of the device.
Equalizer Control; LOW = EQ on, HIGH = EQ bypassed.
Connect to V
CC.
Signal Lock Indication Output. Goes HIGH approximately 38µs after valid parallel data
occurs.
27Mb/s Parallel Data Outputs.
Ground for CMOS blocks of the device.
Power supply for CMOS blocks of the device.
27MHz Clock Output.
NRZI decoding and descrambling control.
LOW = NRZI and SMPTE mode on. HIGH = NRZI and SMPTE mode disabled.
47
48
51
CD
V
CC3
GND
O
-
-
Carrier Detect. Active LOW. Goes LOW when carrier is detected and high when carrier is
lost.
Power supply for Analog and PECL blocks of the device.
Ground for analog and PECL blocks of the device.
DESCRIPTION
5
GENNUM CORPORATION
522 - 14 - 06
Embedded System
京公网安备 11010802033920号
EEWORLD
