Freescale Semiconductor
Technical Data
Document Number: MC56F8006
Rev. 4, 06/2011
MC56F8006/MC56F8002
48-pin LQFP
Case: 932-03
7 x 7 mm
2
32-pin LQFP
Case: 873A-03
7 x 7 mm
2
MC56F8006/MC56F8002
Digital Signal Controller
This document applies to parts marked with 2M53M.
The 56F8006/56F8002 is a member of the 56800E core-based
family of digital signal controllers (DSCs). It combines, on a
single chip, the processing power of a DSP and the
functionality of a microcontroller with a flexible set of
peripherals to create a cost-effective solution. Because of its
low cost, configuration flexibility, and compact program
code, the 56F8006/56F8002 is well-suited for many
applications. It includes many peripherals that are especially
useful for cost-sensitive applications, including:
• Industrial control
• Home appliances
• Smart sensors
• Fire and security systems
• Switched-mode power supply and power management
• Power metering
• Motor control (ACIM, BLDC, PMSM, SR, and stepper)
• Handheld power tools
• Arc detection
• Medical device/equipment
• Instrumentation
• Lighting ballast
The 56800E core is based on a dual Harvard-style architecture
consisting of three execution units operating in parallel, allowing
as many as six operations per instruction cycle. The MCU-style
programming model and optimized instruction set allow
straightforward generation of efficient, compact DSP and control
code. The instruction set is also highly efficient for C compilers
to enable rapid development of optimized control applications.
The 56F8006/56F8002 supports program execution from internal
memories. Two data operands can be accessed from the on-chip
data RAM per instruction cycle. The 56F8006/56F8002 also
offers up to 40 general-purpose input/output (GPIO) lines,
depending on peripheral configuration.
The 56F8006/56F8002 digital signal controller includes up to
16 KB of program flash and 2 KB of unified data/program
28-pin SOIC
Case: 751F-05
7.5 x 18 mm
2
32-pin PSDIP
Case: 1376-02
9 x 28.5 mm
2
RAM. Program flash memory can be independently bulk
erased or erased in small pages of 512 bytes (256 words).
On-chip features include:
• Up to 32 MIPS at 32 MHz core frequency
• DSP and MCU functionality in a unified, C-efficient
architecture
• On-chip memory
– 56F8006: 16 KB (8K x 16) flash memory
– 56F8002: 12 KB (6K x 16) flash memory
– 2 KB (1K x 16) unified data/program RAM
• One 6-channel PWM module
• Two 28-channel, 12-bit analog-to-digital converters
(ADCs)
• Two programmable gain amplifiers (PGA) with gain up to
32x
• Three analog comparators
• One programmable interval timer (PIT)
• One high-speed serial communication interface (SCI) with
LIN slave functionality
• One serial peripheral interface (SPI)
• One 16-bit dual timer (2 x 16 bit timers)
• One programmable delay block (PDB)
• One SMBus compatible inter-integrated circuit (I
2
C) port
• One real time counter (RTC)
• Computer operating properly (COP)/watchdog
• Two on-chip relaxation oscillators — 1 kHz and 8 MHz
(400 kHz at standby mode)
• Crystal oscillator
• Integrated power-on reset (POR) and low-voltage interrupt
(LVI) module
• JTAG/enhanced on-chip emulation (OnCE™) for
unobtrusive, real-time debugging
• Up to 40 GPIO lines
• 28-pin SOIC, 32-pin LQFP, 32-pin PSDIP, and 48-pin
LQFP packages
Freescale reserves the right to change the detail specifications as may be required to permit
improvements in the design of its products.
© Freescale Semiconductor, Inc., 2009–2011. All rights reserved.
Table of Contents
1
2
3
MC56F8006/MC56F8002 Family Configuration . . . . . . . . . . . .3
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
3.1 56F8006/56F8002 Features . . . . . . . . . . . . . . . . . . . . . .4
3.2 Award-Winning Development Environment. . . . . . . . . . .8
3.3 Architecture Block Diagram. . . . . . . . . . . . . . . . . . . . . . .9
3.4 Product Documentation . . . . . . . . . . . . . . . . . . . . . . . .11
Signal/Connection Descriptions . . . . . . . . . . . . . . . . . . . . . . .11
4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
4.2 Pin Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
4.3 56F8006/56F8002 Signal Pins . . . . . . . . . . . . . . . . . . .17
Memory Maps. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
5.2 Program Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
5.3 Data Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
5.4 Interrupt Vector Table and Reset Vector . . . . . . . . . . . .31
5.5 Peripheral Memory-Mapped Registers . . . . . . . . . . . . .32
5.6 EOnCE Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . .33
General System Control Information . . . . . . . . . . . . . . . . . . .34
6.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
6.2 Power Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
6.3 Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
6.4 On-chip Clock Synthesis . . . . . . . . . . . . . . . . . . . . . . . .34
6.5 Interrupt Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
6.6 System Integration Module (SIM) . . . . . . . . . . . . . . . . .37
6.7 PWM, PDB, PGA, and ADC Connections. . . . . . . . . . .38
6.8 Joint Test Action Group (JTAG)/Enhanced On-Chip
Emulator (EOnCE) . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
Security Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
7.1 Operation with Security Enabled. . . . . . . . . . . . . . . . . .40
7.2 Flash Access Lock and Unlock Mechanisms . . . . . . . .40
7.3 Product Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
8.1 General Characteristics . . . . . . . . . . . . . . . . . . . . . . . .
8.2 Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . .
8.3 Thermal Characteristics. . . . . . . . . . . . . . . . . . . . . . . .
8.4 Recommended Operating Conditions . . . . . . . . . . . . .
8.5 DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . .
8.6 Supply Current Characteristics . . . . . . . . . . . . . . . . . .
8.7 Flash Memory Characteristics . . . . . . . . . . . . . . . . . . .
8.8 External Clock Operation Timing. . . . . . . . . . . . . . . . .
8.9 Phase Locked Loop Timing . . . . . . . . . . . . . . . . . . . . .
8.10 Relaxation Oscillator Timing . . . . . . . . . . . . . . . . . . . .
8.11 Reset, Stop, Wait, Mode Select, and Interrupt Timing.
8.12 External Oscillator (XOSC) Characteristics . . . . . . . . .
8.13 AC Electrical Characteristics . . . . . . . . . . . . . . . . . . . .
8.14 COP Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.15 PGA Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.16 ADC Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.17 HSCMP Specifications . . . . . . . . . . . . . . . . . . . . . . . .
8.18 Optimize Power Consumption . . . . . . . . . . . . . . . . . . .
9 Design Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9.1 Thermal Design Considerations . . . . . . . . . . . . . . . . .
9.2 Electrical Design Considerations. . . . . . . . . . . . . . . . .
9.3 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . .
10 Package Mechanical Outline Drawings . . . . . . . . . . . . . . . . .
10.1 28-pin SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . .
10.2 32-pin LQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10.3 48-pin LQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10.4 32-Pin PSDIP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Appendix A
Interrupt Vector Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Appendix B
Peripheral Register Memory Map and Reset Value . . . . . . .
41
42
43
45
46
51
53
53
54
54
56
56
57
65
65
66
68
68
70
70
71
72
73
73
76
79
81
83
83
86
4
5
6
7
8
MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4
2
Freescale Semiconductor
MC56F8006/MC56F8002 Family Configuration
1
MC56F8006/MC56F8002 Family Configuration
Table 1. MC56F8006 Series Device Comparison
MC56F8006
Feature
28-pin
Flash memory size (Kbytes)
RAM size (Kbytes)
Analog comparators (ACMP)
Analog-to-digital converters (ADC)
Unshielded ADC inputs
Shielded ADC inputs
Total number of ADC input pins
1
Programmable gain amplifiers (PGA)
Pulse-width modulator (PWM) outputs
PWM fault inputs
Inter-integrated circuit (IIC)
Serial peripheral interface (SPI)
High speed serial communications interface (SCI)
Programmable interrupt timer (PIT)
Programmable delay block (PDB)
16-bit multi-purpose timers (TMR)
Real-time counter (RTC)
Computer operating properly (COP) timer
Phase-locked loop (PLL)
1 kHz on-chip oscillator
8 MHz (400 kHz at standby mode) on-chip ROSC
Crystal oscillator
Power management controller (PMC)
IEEE 1149.1 Joint Test Action Group (JTAG) interface
Enhanced on-chip emulator (EOnCE) IEEE 1149.1 Joint
Test Action Group (JTAG) interface
1
MC56F8006/MC56F8002 device comparison in
Table 1.
MC56F8002
48-pin
28-pin
12
32-pin
16
2
3
2
6
9
15
7
11
18
2
6
7
17
24
6
9
15
3
4
1
1
1
1
1
2
1
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
4
3
Some ADC inputs share the same pin. See
Table 4.
MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4
Freescale Semiconductor
3
Block Diagram
2
Block Diagram
Figure 1
shows a top-level block diagram of the MC56F8006/MC56F8002 digital signal controller. Package options for this
family are described later in this document. Italics indicate a 56F8002 device parameter.
RESET
4
PWM
6
3
PWM Outputs
Fault Inputs
V
DD
3
V
SS
3
V
DDA
V
SSA
Analog Reg
programmable
delay block
ADCA
PGA/ADC
ADCB
2
2
CMP0
CMP
or
GPIOD
CMP1
Program Controller
and Hardware
Looping Unit
PAB
PDB
CDBR
CDBW
PMC
16-Bit 56800E Core
Data ALU 16 x 16 + 36
36-Bit MAC
Address
Bit
Three 16-bit Input Registers
Generation Unit
Manipulation
Four 36-bit Accumulators
Unit
JTAG/EOnCE
Port or GPIOD
Digital Reg
Low-Voltage
Supervisor
24 Total
R/W Control
Memory
Flash Memory
16 Kbytes flash
12 Kbytes flash
Unified Data /
Program RAM
2KB
XDB2
XAB1
XAB2
PAB
PDB
CDBR
CDBW
System Bus
Control
PIT
2
CMP2
Note:
All pins
are muxed with
other peripheral
pins.
40
GPIO are
muxed with
all other func
pins.
Dual GP Timer
IPBus Bridge
4
Power
Management
Controller
RTC
SPI
SCI
I
2
C
COP/
Watchdog
Interrupt
Controller
System
Integration
Module
Clock ROSC
Generator* OSC
2
4
2
2
Crystal
Oscillator
Figure 1. MC56F8006/MC56F8002 Block Diagram
3
3.1
3.1.1
•
•
•
•
•
•
Overview
56F8006/56F8002 Features
Core
Efficient 16-bit 56800E family digital signal controller (DSC) engine with dual Harvard architecture
As many as 32 million instructions per second (MIPS) at 32 MHz core frequency
155 basic instructions in conjunction with up to 20 address modes
Single-cycle 16
16-bit parallel multiplier-accumulator (MAC)
Four 36-bit accumulators, including extension bits
32-bit arithmetic and logic multi-bit shifter
MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4
4
Freescale Semiconductor
Overview
•
•
•
•
•
•
•
•
•
Parallel instruction set with unique DSP addressing modes
Hardware DO and REP loops
Three internal address buses
Four internal data buses
Instruction set supports DSP and controller functions
Controller-style addressing modes and instructions for compact code
Efficient C compiler and local variable support
Software subroutine and interrupt stack with depth limited only by memory
JTAG/enhanced on-chip emulation (EOnCE) for unobtrusive, processor speed–independent, real-time debugging
3.1.2
•
•
•
Operation Range
1.8 V to 3.6 V operation (power supplies and I/O)
From power-on-reset: approximately 1.9 V to 3.6 V
Ambient temperature operating range:
— –40 °C to 125 °C
3.1.3
•
•
•
Memory
Dual Harvard architecture permits as many as three simultaneous accesses to program and data memory
Flash security and protection that prevent unauthorized users from gaining access to the internal flash
On-chip memory
— 16 KB of program flash for 56F8006 and 12 KB of program flash for 56F8002
— 2 KB of unified data/program RAM
EEPROM emulation capability using flash
•
3.1.4
•
Interrupt Controller
Five interrupt priority levels
— Three user programmable priority levels for each interrupt source: Level 0, 1, 2
— Unmaskable level 3 interrupts include: illegal instruction, hardware stack overflow, misaligned data access, SWI3
instruction. Maskable level 3 interrupts include: EOnCE step counter, EOnCE breakpoint unit, EOnCE trace
buffer
— Lowest-priority software interrupt: level LP
Allow nested interrupt that higher priority level interrupt request can interrupt lower priority interrupt subroutine
The masking of interrupt priority level is managed by the 56800E core
One programmable fast interrupt that can be assigned to any interrupt source
Notification to system integration module (SIM) to restart clock out of wait and stop states
Ability to relocate interrupt vector table
•
•
•
•
•
3.1.5
•
Peripheral Highlights
One multi-function, six-output pulse width modulator (PWM) module
— Up to 96 MHz PWM operating clock
— 15 bits of resolution
— Center-aligned and edge-aligned PWM signal mode
— Phase shifting PWM pulse generation
MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4
Freescale Semiconductor
5
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