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TP2502ND

Description
20V, P-CHANNEL, Si, SMALL SIGNAL, MOSFET
CategoryDiscrete semiconductor    The transistor   
File Size461KB,5 Pages
ManufacturerMicrochip
Websitehttps://www.microchip.com
Download Datasheet Parametric View All

TP2502ND Overview

20V, P-CHANNEL, Si, SMALL SIGNAL, MOSFET

TP2502ND Parametric

Parameter NameAttribute value
Is it Rohs certified?incompatible
MakerMicrochip
package instructionDIE
Reach Compliance Codecompliant
ECCN codeEAR99
Other featuresLOW THRESHOLD
ConfigurationSINGLE WITH BUILT-IN DIODE
Minimum drain-source breakdown voltage20 V
Maximum drain-source on-resistance2 Ω
FET technologyMETAL-OXIDE SEMICONDUCTOR
Maximum feedback capacitance (Crss)25 pF
JESD-30 codeX-XUUC-N
JESD-609 codee0
Number of components1
Number of terminals3
Operating modeENHANCEMENT MODE
Package body materialUNSPECIFIED
Package shapeUNSPECIFIED
Package formUNCASED CHIP
Peak Reflow Temperature (Celsius)NOT SPECIFIED
Polarity/channel typeP-CHANNEL
Certification statusNot Qualified
surface mountYES
Terminal surfaceTIN LEAD
Terminal formNO LEAD
Terminal locationUPPER
Maximum time at peak reflow temperatureNOT SPECIFIED
transistor applicationsSWITCHING
Transistor component materialsSILICON
TP2502
P-Channel Enhancement Mode
Vertical DMOS FETs
Features
Low threshold (-2.4V max.)
High input impedance
Low input capacitance (125pF max.)
Fast switching speeds
Low on-resistance
Free from secondary breakdown
Low input and output leakage
General Description
This low threshold enhancement-mode (normally-off) tran-
sistor utilizes a vertical DMOS structure and Supertex’s well-
proven silicon-gate manufacturing process. This combination
produces a device with the power handling capabilities of bipolar
transistors and with the high input impedance and positive
temperature coefficient inherent in MOS devices. Characteristic
of all MOS structures, this device is free from thermal runaway
and thermally-induced secondary breakdown.
Supertex’s vertical DMOS FETs are ideally suited to a wide
range of switching and amplifying applications where very
low threshold voltage, high breakdown voltage, high input
impedance, low input capacitance, and fast switching speeds
are desired.
Applications
Logic level interfaces - ideal for TTL and CMOS
Solid state relays
Battery operated systems
Photo voltaic drives
Analog switches
General purpose line drivers
Telecom switches
Ordering Information
Device
TP2502
Package Options
TO-243AA (SOT-89)
TP2502N8-G
Die*
TP2502ND
BV
DSS
/BV
DGS
(V)
R
DS(ON)
(Ω)
V
GS(TH)
(max)
(V)
I
D(ON)
(min)
(A)
-20
2.0
-2.4
-2.0
-G indicates package is RoHS compliant (‘Green’)
* MIL visual screening available.
Pin Configuration
DRAIN
Absolute Maximum Ratings
Parameter
Drain-to-source voltage
Drain-to-gate voltage
Gate-to-source voltage
Operating and storage temperature
Soldering temperature*
Value
BV
DGS
±20V
-55°C to +150°C
300°C
BV
DSS
GATE
SOURCE
DRAIN
TO-243AA (SOT-89) (N8)
Product Marking
TP5LW
W = Code for week sealed
= “Green” Packaging
Package may or may not include the following marks: Si or
TO-243AA (SOT-89) (N8)
Absolute Maximum Ratings are those values beyond which damage to the device may
occur. Functional operation under these conditions is not implied. Continuous operation
of the device at the absolute rating level may affect device reliability. All voltages are
referenced to device ground.
*
Distance of 1.6 mm from case for 10 seconds.
1235 Bordeaux Drive, Sunnyvale, CA 94089
Tel: 408-222-8888
www.supertex.com
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Index Files: 147  1159  1079  1929  1415  3  24  22  39  29 
Datasheet   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
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