IS66WV25616ALL-70BLI datasheet, PDF

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IS66WV25616ALL-70BLI: DescriptionPseudo Static RAM, 256KX16, 70ns, CMOS, PBGA48, 8 X 6 MM, LEAD FREE, MO-207, TFBGA-48; Categorystorage storage; File Size428KB，16 Pages; ManufacturerABLIC

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IS66WV25616ALL-70BLI Overview

Pseudo Static RAM, 256KX16, 70ns, CMOS, PBGA48, 8 X 6 MM, LEAD FREE, MO-207, TFBGA-48

IS66WV25616ALL-70BLI Parametric

Parameter Name	Attribute value
Maker	ABLIC
Parts packaging code	DSBGA
package instruction	TFBGA,
Contacts	48
Reach Compliance Code	unknown
ECCN code	3A991.B.2.A
Maximum access time	70 ns
JESD-30 code	R-PBGA-B48
length	8 mm
memory density	4194304 bit
Memory IC Type	PSEUDO STATIC RAM
memory width	16
Number of functions	1
Number of terminals	48
word count	262144 words
character code	256000
Operating mode	ASYNCHRONOUS
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
organize	256KX16
Package body material	PLASTIC/EPOXY
encapsulated code	TFBGA
Package shape	RECTANGULAR
Package form	GRID ARRAY, THIN PROFILE, FINE PITCH
Parallel/Serial	PARALLEL
Certification status	Not Qualified
Maximum seat height	1.2 mm
Maximum supply voltage (Vsup)	1.95 V
Minimum supply voltage (Vsup)	1.7 V
Nominal supply voltage (Vsup)	1.8 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal form	BALL
Terminal pitch	0.75 mm
Terminal location	BOTTOM
width	6 mm

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IS66WV25616ALL

IS66WV25616BLL

4Mb LOW VOLTAGE,

ULTRA LOW POWER PSEUDO CMOS STATIC RAM

JANUARY 2010

FEATURES

• High-speed access time: 55ns

• CMOS low power operation

– mW (typical) operating

– µW (typical) CMOS standby

• Single power supply

– 1.7V--1.95V V

(66WV25616ALL)

(70ns)

– 2.5V--3.6V V

(66WV25616BLL) (55ns)

• Three state outputs

• Data control for upper and lower bytes

• Industrial temperature available

• Lead-free available

bit static RAMs organized as 256K words by 16 bits. It is

fabricated using

ISSI

's high-performance CMOS technology.

This highly reliable process coupled with innovative circuit

design techniques, yields high-performance and low power

consumption devices.

When

CS1

is HIGH (deselected) or when CS2 is LOW

(deselected) or both

and

are HIGH, the device

assumes a standby mode at which the power dissipation

can be reduced down with CMOS input levels.

Easy memory expansion is provided by using Chip Enable

and Output Enable inputs. The active LOW Write Enable

(WE)

controls both writing and reading of the memory. A

data byte allows Upper Byte (UB) and Lower Byte (LB)

access.

The IS66WV25616ALL/BLL is packaged in the JEDEC

standard 48-pin mini BGA (6mm x 8mm) and 44-Pin TSOP

(TYPE II). The device is aslo available for die sales.

DESCRIPTION

The

ISSI

IS66WV25616ALL/BLL is a high-speed, 4M

FUNCTIONAL BLOCK DIAGRAM

A0-A17

DECODER

256K x 16

MEMORY ARRAY

GND

I/O0-I/O7

Lower Byte

I/O8-I/O15

Upper Byte

I/O

DATA

CIRCUIT

COLUMN I/O

CS2

CS1

CONTROL

CIRCUIT

liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on

any published information and before placing orders for products.

Integrated Silicon Solution, Inc. — www.issi.com

Rev. A

12/02/09

IS66WV25616ALL-70BLI Related Products

	IS66WV25616ALL-70BLI	IS66WV25616BLL-55BLI	IS66WV25616ALL-70TLI	IS66WV25616BLL-55TLI
Description	Pseudo Static RAM, 256KX16, 70ns, CMOS, PBGA48, 8 X 6 MM, LEAD FREE, MO-207, TFBGA-48	Pseudo Static RAM, 256KX16, 55ns, CMOS, PBGA48, 8 X 6 MM, LEAD FREE, MO-207, TFBGA-48	Pseudo Static RAM, 256KX16, 70ns, CMOS, PDSO44, 0.400 INCH, LEAD FREE, TSOP2-44	Pseudo Static RAM, 256KX16, 55ns, CMOS, PDSO44, 0.400 INCH, LEAD FREE, TSOP2-44
Maker	ABLIC	ABLIC	ABLIC	ABLIC
Parts packaging code	DSBGA	DSBGA	TSOP2	TSOP2
package instruction	TFBGA,	8 X 6 MM, LEAD FREE, MO-207, TFBGA-48	0.400 INCH, LEAD FREE, TSOP2-44	0.400 INCH, LEAD FREE, TSOP2-44
Contacts	48	48	44	44
Reach Compliance Code	unknown	unknown	unknown	unknown
ECCN code	3A991.B.2.A	3A991.B.2.A	3A991.B.2.A	3A991.B.2.A
Maximum access time	70 ns	55 ns	70 ns	55 ns
JESD-30 code	R-PBGA-B48	R-PBGA-B48	R-PDSO-G44	R-PDSO-G44
length	8 mm	8 mm	18.41 mm	18.41 mm
memory density	4194304 bit	4194304 bit	4194304 bit	4194304 bit
Memory IC Type	PSEUDO STATIC RAM	PSEUDO STATIC RAM	PSEUDO STATIC RAM	PSEUDO STATIC RAM
memory width	16	16	16	16
Number of functions	1	1	1	1
Number of terminals	48	48	44	44
word count	262144 words	262144 words	262144 words	262144 words
character code	256000	256000	256000	256000
Operating mode	ASYNCHRONOUS	ASYNCHRONOUS	ASYNCHRONOUS	ASYNCHRONOUS
Maximum operating temperature	85 °C	85 °C	85 °C	85 °C
Minimum operating temperature	-40 °C	-40 °C	-40 °C	-40 °C
organize	256KX16	256KX16	256KX16	256KX16
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	TFBGA	TFBGA	TSOP2	TSOP2
Package shape	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR
Package form	GRID ARRAY, THIN PROFILE, FINE PITCH	GRID ARRAY, THIN PROFILE, FINE PITCH	SMALL OUTLINE, THIN PROFILE	SMALL OUTLINE, THIN PROFILE
Parallel/Serial	PARALLEL	PARALLEL	PARALLEL	PARALLEL
Certification status	Not Qualified	Not Qualified	Not Qualified	Not Qualified
Maximum seat height	1.2 mm	1.2 mm	1.2 mm	1.2 mm
Maximum supply voltage (Vsup)	1.95 V	3.6 V	1.95 V	3.6 V
Minimum supply voltage (Vsup)	1.7 V	2.5 V	1.7 V	2.5 V
Nominal supply voltage (Vsup)	1.8 V	3 V	1.8 V	3 V
surface mount	YES	YES	YES	YES
technology	CMOS	CMOS	CMOS	CMOS
Temperature level	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL
Terminal form	BALL	BALL	GULL WING	GULL WING
Terminal pitch	0.75 mm	0.75 mm	0.8 mm	0.8 mm
Terminal location	BOTTOM	BOTTOM	DUAL	DUAL
width	6 mm	6 mm	10.16 mm	10.16 mm

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