K4B1G04(08/16)46C
1Gb DDR3 SDRAM
Table Contents
1.0 Ordering Information ....................................................................................................................................................4
2.0 Key Features .................................................................................................................................................................4
3.0 Package pinout/Mechanical Dimension & Addressing .............................................................................................5
3.1 x4 Package Pinout (Top view) : 94ball FBGA Package(78balls + 16 balls of support balls)
..........................................5
3.2 x8 Package Pinout (Top view) : 94ball FBGA Package(78balls + 16 balls of support balls)
..........................................6
3.3 x16 Package Pinout (Top view) : 112ball FBGA Package(96balls + 16 balls of support balls)
......................................7
3.4 FBGA Package Dimension (x4)
...................................................................................................................................8
3.5 FBGA Package Dimension (x8)
...................................................................................................................................9
3.6 FBGA Package Dimension (x16)
...............................................................................................................................10
4.0 Input/Output Functional Description ........................................................................................................................11
5.0 DDR3 SDRAM Addressing .........................................................................................................................................12
6.0 Absolute Maximum Ratings .......................................................................................................................................14
6.1 Absolute Maximum DC Ratings
................................................................................................................................14
6.2 DRAM Component Operating Temperature Range
....................................................................................................14
7.0 AC & DC Operating Conditions .................................................................................................................................14
7.1 Recommended DC operating Conditions (SSTL_1.5)
.................................................................................................14
8.0 AC & DC Input Measurement Levels .........................................................................................................................15
8.1 AC and DC Logic input levels for single-ended signals
.............................................................................................15
8.2 Differential swing requirement for differntial signals
................................................................................................16
8.2.1 Single-ended requirements for differential signals
............................................................................................17
8.3 AC and DC logic input levels for Differential Signals
.................................................................................................18
8.4 Differential Input Cross Point Voltage
.......................................................................................................................18
8.5 Slew rate definition for Single Ended Input Signals
...................................................................................................19
8.5.1 Input Slew Rate for Input Setup Time (tIS) and Data Setup Time (tDS)
...............................................................19
8.5.2 Input Slew Rate for Input Hold Time (tIH) and Data Hold Time (tDH)
..................................................................19
8.6 Slew rate definition for Differential Input Signals
......................................................................................................19
9.0 AC and DC Output Measurement Levels .................................................................................................................. 20
9.1 Single Ended AC and DC Output Levels
....................................................................................................................20
9.2 Differential AC and DC Output Levels
.......................................................................................................................20
9.3.Single Ended Output Slew Rate
................................................................................................................................ 21
9.4 Differential Output Slew Rate
....................................................................................................................................21
9.5 Reference Load for AC Timing and Output Slew Rate
................................................................................................22
9.6 Overshoot/Undershoot Specification
........................................................................................................................23
9.6.1 Address and Control Overshoot and Undershoot specifications
.......................................................................23
9.6.2 Clock, Data, Strobe and Mask Overshoot and Undershoot specifications
..........................................................23
9.7 34 ohm Output Driver DC Electrical Characteristics
..................................................................................................24
9.7.1 Output Drive Temperature and Voltage sensitivity
............................................................................................25
9.8 On-Die Termination (ODT) Levels and I-V Characteristics
..........................................................................................25
9.8.1 ODT DC electrical characteristics
.....................................................................................................................26
9.8.2 ODT Temperature and Voltage sensitivity
......................................................................................................... 27
9.9 ODT Timing Definitions
............................................................................................................................................ 28
9.9.1 Test Load for ODT Timings
............................................................................................................................... 28
9.9.2 ODT Timing Definition
......................................................................................................................................28
10.0 Idd Specification Parameters and Test Conditions ...............................................................................................31
10.1 IDD Measurement Conditions
.................................................................................................................................31
10.2 IDD Specifications
..................................................................................................................................................41
11.0 Input/Output Capacitance ........................................................................................................................................43
12.0 Electrical Characteristics and AC timing for DDR3-800 to DDR3-1600 ................................................................44
12.1 Clock specification
.................................................................................................................................................44
12.2 Clock Jitter Specification
........................................................................................................................................45
12.3 Refresh Parameters by Device Density
...................................................................................................................46
12.4 Standard Speed Bins
..............................................................................................................................................46
13.0 Timing Parameters by Speed Grade ....................................................................................................................... 48
Page 3 of 63
Rev. 1.0 June 2007
K4B1G04(08/16)46C
1.0 Ordering Information
[ Table 1 ] Samsung DDR3 ordering information table
Organization
256Mx4
128Mx8
64Mx16
DDR3-800 (6-6-6)
K4B1G0446C-ZCF7
K4B1G0846C-ZCF7
K4B1G1646C-ZCF7
DDR3-1066 (7-7-7/8-8-8)
K4B1G0446C-CF8/G8
K4B1G0846C-CF8/G8
K4B1G1646C-CF8/G8
1Gb DDR3 SDRAM
DDR3-1333 (8-8-8/9-9-9)
K4B1G0446C-ZCG9/H9
K4B1G0846C-ZCG9/H9
K4B1G1646C-ZCG9/H9
Package
94 FBGA
94 FBGA
112 FBGA
Note :
1. Speed bin is in order of CL-tRCD-tRP.
2. x4/x8/x16 Package - including 16 support balls
2.0 Key Features
[ Table 2 ] 1Gb DDR3 C-die Speed bins
Speed
tCK(min)
CAS Latency
tRCD(min)
tRP(min)
tRAS(min)
tRC(min)
DDR3-800
6-6-6
2.5
6
15
15
37.5
52.5
7
13.125
13.125
37.5
50.625
7-7-7
1.875
8
15
15
37.5
52.5
8
12
12
36
48
DDR3-1066
8-8-8
8-8-8
1.5
9
13.5
13.5
36
49.5
DDR3-1333
9-9-9
Unit
ns
tCK
ns
ns
ns
ns
• JEDEC standard 1.5V ± 0.075V Power Supply
• VDDQ = 1.5V ± 0.075V
• 400 MHz f
CK
for 800Mb/sec/pin, 533MHz f
CK
for 1066Mb/sec/pin,
667MHz f
CK
for 1333Mb/sec/pin
• 8 Banks
• Posted CAS
• Programmable CAS Latency: 5, 6, 7, 8, 9, 10, (11 for high density
only)
• Programmable Additive Latency: 0, CL-2 or CL-1 clock
• Programmable CAS Write Latency (CWL) = 5 (DDR3-800), 6
(DDR3-1066), 7 (DDR3-1333)
• 8-bit pre-fetch
• Burst Length: 8 (Interleave without any limit, sequential with starting
address “000” only), 4 with tCCD = 4 which does not allow seamless
read or write [either On the fly using A12 or MRS]
• Bi-directional Differential Data-Strobe
• Internal(self) calibration : Internal self calibration through ZQ pin
(RZQ : 240 ohm ± 1%)
• On Die Termination using ODT pin
• Average Refresh Period 7.8us at lower than T
CASE
85×C, 3.9us at
85×C < T
CASE
< 95 ×C
• Asynchronous Reset
• Package : 94 balls FBGA - x4/x8 (with 16 support balls)
112 balls FBGA - x16 (with 16 support balls)
• All of Lead-free products are compliant for RoHS
Note : 1. The functionality described and the timing specifications included
in this data sheet are for the DLL Enabled mode of operation.
2. 1066Mbps CL7 doesn’t have back-ward compatibility with
800Mbps CL5
The 1Gb DDR3 SDRAM C-die is organized as a 32Mbit x 4/16Mbit x 8/
8Mbit x 16 I/Os x 8banks device. This synchronous device achieves high
speed double-data-rate transfer rates of up to 1333Mb/sec/pin (DDR3-
1333) for general applications.
The chip is designed to comply with the following key DDR3 SDRAM fea-
tures such as posted CAS, Programmable CWL, Internal (Self) Calibra-
tion, On Die Termination using ODT pin and Asynchronous Reset .
All of the control and address inputs are synchronized with a pair of exter-
nally supplied differential clocks. Inputs are latched at the crosspoint of dif-
ferential clocks (CK rising and CK falling). All I/Os are synchronized with a
pair of bidirectional strobes (DQS and DQS) in a source synchronous fash-
ion. The address bus is used to convey row, column, and bank address
information in a RAS/CAS multiplexing style. The DDR3 device operates
with a single 1.5V ± 0.075V power supply and 1.5V ± 0.075V VDDQ.
The 1Gb DDR3 device is available in 94ball FBGAs(x4/x8) and 112ball
FBGA(x16)
Note : This data sheet is an abstract of full DDR3 specification and does not cover the common features which are described in “DDR3 SDRAM Device
Operation & Timing Diagram”.
Page 4 of 63
Rev. 1.0 June 2007
Analog electronics
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