K4T51163QE-ZCD5 datasheet, PDF

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K4T51163QE-ZCD5: DescriptionDDR DRAM, 32MX16, 0.5ns, CMOS, PBGA90; Categorystorage storage; File Size947KB，45 Pages; ManufacturerSAMSUNG; Websitehttp://www.samsung.com/Products/Semiconductor/; Environmental Compliance

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K4T51163QE-ZCD5 Overview

DDR DRAM, 32MX16, 0.5ns, CMOS, PBGA90

K4T51163QE-ZCD5 Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	SAMSUNG
package instruction	FBGA, BGA90,9X15,32
Reach Compliance Code	compliant
Maximum access time	0.5 ns
Maximum clock frequency (fCLK)	266 MHz
I/O type	COMMON
interleaved burst length	4,8
JESD-30 code	R-PBGA-B90
JESD-609 code	e1
memory density	536870912 bit
Memory IC Type	DDR DRAM
memory width	16
Humidity sensitivity level	3
Number of terminals	90
word count	33554432 words
character code	32000000
Maximum operating temperature	95 °C
Minimum operating temperature
organize	32MX16
Output characteristics	3-STATE
Package body material	PLASTIC/EPOXY
encapsulated code	FBGA
Encapsulate equivalent code	BGA90,9X15,32
Package shape	RECTANGULAR
Package form	GRID ARRAY, FINE PITCH
Peak Reflow Temperature (Celsius)	260
power supply	1.8 V
Certification status	Not Qualified
refresh cycle	8192
Continuous burst length	4,8
Maximum standby current	0.008 A
Maximum slew rate	0.24 mA
Nominal supply voltage (Vsup)	1.8 V
surface mount	YES
technology	CMOS
Temperature level	OTHER
Terminal surface	Tin/Silver/Copper (Sn96.5Ag3.0Cu0.5)
Terminal form	BALL
Terminal pitch	0.8 mm
Terminal location	BOTTOM
Maximum time at peak reflow temperature	NOT SPECIFIED

K4T51163QE-ZCD5 Preview

K4T51043QE

K4T51083QE

K4T51163QE

DDR2 SDRAM

512Mb E-die DDR2 SDRAM Specification

60FBGA & 84FBGA with Pb-Free

(RoHS compliant)

INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS,

AND IS SUBJECT TO CHANGE WITHOUT NOTICE.

NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE,

EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE,

TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL

INFORMATION IN THIS DOCUMENT IS PROVIDED

ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND.

1. For updates or additional information about Samsung products, contact your nearest Samsung office.

2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar

applications where Product failure couldresult in loss of life or personal or physical harm, or any military or

defense application, or any governmental procurement to which special terms or provisions may apply.

* Samsung Electronics reserves the right to change products or specification without notice.

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DDR2 SDRAM

Table of Contents

1.0 Ordering Information ....................................................................................................................4

2.0 Key Features .................................................................................................................................4

3.0 Package Pinout/Mechanical Dimension & Addressing .............................................................5

3.1 x4 package pinout (Top View) : 60ball FBGA Package

........................................................................5

3.2 x8 package pinout (Top View) : 60ball FBGA Package

.........................................................................6

3.3 x16 package pinout (Top View) : 84ball FBGA Package

.......................................................................7

3.4 FBGA Package Dimension(x4/x8)

.....................................................................................................8

3.5 FBGA Package Dimension(x16)

.......................................................................................................9

4.0 Input/Output Functional Description ........................................................................................10

5.0 DDR2 SDRAM Addressing .........................................................................................................11

6.0 Absolute Maximum DC Ratings .................................................................................................12

7.0 AC & DC Operating Conditions .................................................................................................12

.......................................................................12

7.2 Operating Temperature Condition

..................................................................................................13

7.3 Input DC Logic Level

....................................................................................................................13

7.4 Input AC Logic Level

....................................................................................................................13

7.5 AC Input Test Conditions

..............................................................................................................13

7.6 Differential input AC logic Level

.....................................................................................................14

7.7 Differential AC output parameters

..................................................................................................14

8.0 ODT DC electrical characteristics .............................................................................................14

9.0 OCD default characteristics ......................................................................................................15

10.0 IDD Specification Parameters and Test Conditions ..............................................................16

11.0 DDR2 SDRAM IDD Spec ...........................................................................................................18

12.0 Input/Output capacitance .........................................................................................................19

13.0 Electrical Characteristics & AC Timing for DDR2-800/667/533/400 ......................................19

13.1 Refresh Parameters by Device Density

........................................................................................19

13.2 Speed Bins and CL, tRCD, tRP, tRC and tRAS for Corresponding Bin

.............................................19

13.3 Timing Parameters by Speed Grade

............................................................................................20

14.0 General notes, which may apply for all AC parameters ........................................................22

15.0 Specific Notes for dedicated AC parameters ..........................................................................23

7.1 Recommended DC Operating Conditions (SSTL - 1.8)

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DDR2 SDRAM

Year

2006

2007

- Initial Release

- Revised the IDD values

- Added DDR2-800 CL6

- Added the detailed explanation on the notes for AC parameters

- Corrected Typo

- Added data setup and hold time derating values for single-end DQS

- Corrected Typo

- Updated general and specific notes for AC parameters

History

Revision History

Revision

1.0

1.1

1.2

1.3

1.4

1.5

1.6

1.7

1.8

Month

March

August

September

October

March

April

June

July

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K4T51083QE

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1.0 Ordering Information

Org.

128Mx4

64Mx8

32Mx16

DDR2-800 5-5-5

K4T51043QE-ZC(L)E7

K4T51083QE-ZC(L)E7

K4T51163QE-ZC(L)E7

DDR2-800 6-6-6

K4T51043QE-ZC(L)F7

K4T51083QE-ZC(L)F7

K4T51163QE-ZC(L)F7

DDR2-667 5-5-5

K4T51043QE-ZC(L)E6

K4T51083QE-ZC(L)E6

K4T51163QE-ZC(L)E6

DDR2-533 4-4-4

DDR2 SDRAM

DDR2-400 3-3-3

Package

60 FBGA

84 FBGA

K4T51043QE-ZC(L)D5 K4T51043QE-ZC(L)CC

K4T51083QE-ZC(L)D5 K4T51083QE-ZC(L)CC

K4T51163QE-ZC(L)D5 K4T51163QE-ZC(L)CC

Note :

1. Speed bin is in order of CL-tRCD-tRP

2. RoHS Compliant

2.0 Key Features

Speed

CAS Latency

tRCD(min)

tRP(min)

tRC(min)

DDR2-800 5-5-5

12.5

57.5

DDR2-800 6-6-6

DDR2-667 5-5-5

DDR2-533 4-4-4

DDR2-400 3-3-3

Units

tCK

• JEDEC standard 1.8V ± 0.1V Power Supply

• VDDQ = 1.8V ± 0.1V

• 200 MHz f

for 400Mb/sec/pin, 267MHz f

for 533Mb/sec/

pin, 333MHz f

for 667Mb/sec/pin, 400MHz f

for 800Mb/

sec/pin

• 4 Banks

• Posted CAS

• Programmable CAS Latency: 3, 4, 5, 6

• Programmable Additive Latency: 0, 1 , 2 , 3, 4 , 5

• Write Latency(WL) = Read Latency(RL) -1

• Burst Length: 4 , 8(Interleave/nibble sequential)

• Programmable Sequential / Interleave Burst Mode

• Bi-directional Differential Data-Strobe (Single-ended data-

strobe is an optional feature)

• Off-Chip Driver(OCD) Impedance Adjustment

• On Die Termination

• Special Function Support

-PASR(Partial Array Self Refresh)

-50ohm ODT

-High Temperature Self-Refresh rate enable

• Average Refresh Period 7.8us at lower than T

CASE

85°C,

3.9us at 85°C < T

CASE

< 95

°C

• All of Lead-free products are compliant for RoHS

The 512Mb DDR2 SDRAM is organized as a 32Mbit x 4 I/Os x 4

banks, 16Mbit x 8 I/Os x 4banks or 8Mbit x 16 I/Os x 4 banks

device. This synchronous device achieves high speed double-

data-rate transfer rates of up to 800Mb/sec/pin (DDR2-800) for

general applications.

The chip is designed to comply with the following key DDR2

SDRAM features such as posted CAS with additive latency, write

latency = read latency -1, Off-Chip Driver(OCD) impedance

adjustment and On Die Termination.

All of the control and address inputs are synchronized with a pair

of externally supplied differential clocks. Inputs are latched at the

crosspoint of differential clocks (CK rising and CK falling). All I/Os

are synchronized with a pair of bidirectional strobes (DQS and

DQS) in a source synchronous fashion. The address bus is used

to convey row, column, and bank address information in a RAS/

CAS multiplexing style. For example, 512Mb(x4) device receive

14/11/2 addressing.

The 512Mb DDR2 device operates with a single 1.8V ± 0.1V

power supply and 1.8V ± 0.1V VDDQ.

The 512Mb DDR2 device is available in 60ball FBGAs(x4/x8) and

in 84ball FBGAs(x16).

Note :

The functionality described and the timing specifications included in

this data sheet are for the DLL Enabled mode of operation.

Note :

This data sheet is an abstract of full DDR2 specification and does not cover the common features which are described in “Samsung’s DDR2

SDRAM Device Operation & Timing Diagram”

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3.0 Package Pinout/Mechanical Dimension & Addressing

DDR2 SDRAM

3.1 x4 package pinout (Top View) : 60ball FBGA Package

VDD

VDDQ

VDDL

VSSQ

DQ1

VSSQ

VREF

CKE

VSS

VDDQ

DQ3

VSS

BA1

VSSQ

DQS

VDDQ

DQ2

VSSDL

RAS

CAS

A11

DQS

VSSQ

DQ0

VSSQ

A13

VDDQ

VDD

ODT

BA0

A10/AP

VDD

VSS

VDD

A12

Note :

1. Pin B3 has identical capacitance as pin B7.

2. VDDL and VSSDL are power and ground for the DLL.

Ball Locations (x4)

: Populated Ball

+ : Depopulated Ball

Top View

(See the balls through the Package)

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Rev. 1.8 July 2007

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