512K x 8 SRAM
MSM8512 - 020/025/35
11403 West Bernado Court, Suite 100, San Diego, CA 92127.
Tel No: (619) 674 2233, Fax No: (619) 674 2230
Issue 1.0 : January 1999
Description
The MSM8512 is a 4Mbit monolithic SRAM organised
as 512K x 8 with access times from 20ns to 35ns
available. The device is available in two 32 pin ceramic
surface mount packages. The device has a low power
standby version which supports data retention mode
and is directly TTL compatible.
524,288 x 8 CMOS Static RAM
Features
Fast Access Times of 020/025/35 ns
High Density Packages.
Operating Power 950 mW (nom)
Standby Power
75 mW (nom) -L version
Low voltage data retention.
Completely Static Operation
Directly TTL compatible
May be processed in accordance with
MIL-STD-883C
•
•
•
•
All versions can be screened in accordance with MIL- •
•
STD-883C.
•
•
Block Diagram
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
D0
D7
WE
OE
CS
X ADDRESS BUFFER
Pin Definition
D6
D5
D4
D3
GND
D2
ROW DECODER
4,194,304
BIT
MEMORY
ARRAY
D7
CS
A10
OE
A11
A9
A8
A13
WE
21
22
23
24
25
26
27
28
29
20 19 18 17 16 15 14
13
12
11
10
9
8
7
6
5
D0
A0
A1
A2
A3
A4
A5
A6
A7
J/ W
I/O
BUFFER
COLUMN I/O
COLUMN DECODER
Y ADDRESS BUFFER
A10
A11
A12
A13
A14
A15
A16
A17
A18
1
30 31 32
2 3 4
A17
VCC
A15
A18
A16
Package Details
Pin Count
32
32
Descripion
JLCC Package
LCC Package
Package Type
J
W
Pin Functions
A0~A18
Address Inputs
D0~7
Data Input/Output
CS
Chip Select
OE
Output Enable
WE
Write Enable
Power (+5V)
V
CC
GND
Ground
A14
A12
D1
ISSUE 1.0 : January 1999
MSM8512 - 020/025/30
DC OPERATING CONDITIONS
Absolute Maximum Ratings
(1)
Voltage on any pin relative to V
SS (2)
Power Dissipation
Storage Temperature
V
T
P
T
T
STG
-0.5
-55
to
1
to
+7.0
+150
V
W
O
C
Notes : (1) Stresses above those listed may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.
Recommended Operating Conditions
Parameter
Supply Voltage
Input High Voltage
Input Low Voltage
Operating Temperature
Symbol
V
CC
V
IH
V
IL
T
A
T
AI
T
AM
min
4.5
2.2
-0.3
0
-40
-55
typ
5.0
-
-
-
-
-
max
5.5
6.0
0.8
70
85
125
unit
V
V
V
o
C
o
C
o
C
(I suffix)
(M, MB suffix)
DC Electrical Characteristics
(V
CC
= 5.0V±10%, T
A
=-55°C to +125°C)
Parameter
Input Leakage Current
Output Leakage Current
Symbol Test Condition
I
LI
I
LO
V
IN
=0V to V
CC
CS=V
IH
, V
I/O
=0V to V
CC
, OE=V
IH
or WE=V
IL
CS=V
IL
, V
IN
=V
IH
or V
IL
I
I/O
=0mA, min cycle, duty=100%
Min Cycle, CS=V
IH
CS
≥
V
CC
-0.2V, V
IN
≥
V
CC
-0.2V or 0.2V
≥
V
IN
f=0MHZ
min
-2
-2
-
-
-
typ
-
-
-
-
-
-
-
max
2
2
185
65
15
0.4
-
Unit
µA
µA
mA
mA
mA
V
V
Operating Supply Current I
CC1
Standby Supply Current
-L version only
Output Voltage
I
SB
I
SB1
V
OL
I
OL
=8.0mA
V
OH
I
OH
=-4.0mA
-
2.4
Capacitance
(V
CC
=5V±10%,T
A
=25°C)
Parameter
Input Capacitance:
I/O Capacitance:
Symbol
C
IN
C
I/O
Test Condition
V
IN
= 0V
V
I/O
= 0V
typ
-
-
max
8
8
Unit
pF
pF
Note : This parameter is sampled and not 100% tested.
AC Test Conditions
* Input pulse levels : 0V to 3.0V
* Input rise and fall times : 3ns
* Input and Output timing reference levels: 1.5V
* Output load: See Load Diagram
* V
cc
=5V±10%
Output Load
I/O Pin
166Ω
1.76V
30pF
2
MSM8512 - 020/025/35
ISSUE 1.0 : January 1999
Low V
cc
Data Retention Characteristics - L Version Only
(T
A
=-55°C to +125
o
C)
Parameter
V
CC
for Data Retention
Data Retention Current
Chip Deselect to Data Retention
Operation Recovery Time
Symbol Test Condition
V
DR
I
CCDR
t
CDR
t
R
CS
≥
V
CC
-0.2V
V
CC
=3.0V, CS
≥
V
CC
-0.2V,
See Retention Waveform
See Retention Waveform
min
2.0
-
0
5
typ
-
-
-
-
max
5.5
8
-
-
Unit
V
mA
ns
ms
AC OPERATING CONDITIONS
Read Cycle
Parameter
Symbol
t
RC
t
AA
t
ACS
t
OE
t
OH
t
CLZ
t
OLZ
t
CHZ
t
OHZ
20
min max
20
-
-
-
5
5
0
-
0
-
20
20
10
-
-
-
10
10
25
min max
25
-
-
-
5
5
0
0
0
-
25
25
15
-
-
-
10
10
35
min max
35
-
-
-
5
5
0
0
0
-
35
35
15
-
-
-
10
10
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
Read Cycle Time
Address Access Time
Chip Select Access Time
Output Enable to Output Valid
Output Hold from Address Change
Chip Selection to Output in Low Z
Output Enable to Output in Low Z
Chip Deselection to Output in High Z
(3)
Output Disable to Output in High Z
(3)
Write Cycle
20
Parameter
Write Cycle Time
Chip Selection to End of Write
Address Valid to End of Write
Address Setup Time
Write Pulse Width
Write Recovery Time
Write to Output in High Z
Data to Write Time Overlap
Data Hold from Write Time
Output Active from End of Write
25
max
-
-
-
-
-
-
10
-
-
-
35
max
-
-
-
-
-
-
10
-
-
-
Symbol
t
WC
t
CW
t
AW
t
AS
t
WP
t
WR
t
WHZ
t
DW
t
DH
t
OW
min
20
15
15
0
15
0
0
10
0
5
min
25
15
15
0
15
0
0
10
0
5
min
35
15
15
0
15
0
0
10
0
5
max
-
-
-
-
-
-
10
-
-
-
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
3
ISSUE 1.0 : January 1999
MSM8512 - 020/025/30
Read Cycle Timing Waveform
(1,2)
t
Address
RC
t
AA
OE
t
OE
t
OLZ
CS
t
OH
t
CLZ
t
ACS
t
CHZ(3)
t
OHZ(3)
D0~7
High-Z
Data Valid
Notes:
(1) During the Read Cycle, WE is high.
(2) Address valid prior to or coincident with CS transition Low.
(3) t
CHZ
and t
OHZ
are defined as the time at which the outputs achieve the open circuit conditions and are not referenced
to output voltage levels. These parameters are sampled and not 100% tested.
Write Cycle No.1 Timing Waveform
t
WC
Address
OE
t
AS(3)
t
AW
t
CW(4)
(6)
t
WR
(2)
CS
t
WP(1)
WE
t
OHZ(3,9)
D0~7 out
High-Z
t
DW
t
OW
t
DH
D0~7 in
High-Z
4
MSM8512 - 020/025/35
ISSUE 1.0 : January 1999
Write Cycle No.2 Timing Waveform
(5)
t
WC
Address
t
CW
CS
(6)
(4)
t
AW
t
WP(1)
WE
t
WR(2)
t
AS(3)
t
WHZ(3,9)
t
OW
High-Z
t
DW
t
OH
(8)
(7)
D0~7 out
t
DH
D0~7 in
High-Z
AC Characteristics Notes
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
A write occurs during the overlap (t
WP
) of a low CS and a low WE.
t
WR
is measured from the earlier of CS or WE going high to the end of write cycle.
During this period, I/O pins are in the output state. Input signals out of phase must not be applied.
If the CS low transition occurs simultaneously with the WE low transition or after the WE low transition, outputs
remain in a high impedance state.
OE is continuously low. (OE=V
IL
)
D
OUT
is in the same phase as written data of this write cycle.
D
OUT
is the read data of next address.
If CS is low during this period, I/O pins are in the output state. Input signals out of phase must not be applied.
t
WHZ
and t
OHZ
are defined as the time at which the outputs achieve the open circuit conditions and are not
referenced to output voltage levels. These parameters are sampled and not 100% tested.
Low V
CC
Data Retention Timing Waveform
Vcc
DATA RETENTION MODE
4.5V
4.5V
t
CDR
2.2V
t
R
2.2V
V
DR
CS
0V
CS>Vcc-0.2V
5
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