F85226AF
F85226AF
LPC to ISA Bridge
Release Date: July, 2008
Revision: V0.20P
Fintek
Feature Integration Technology Inc.
F85226AF
F85226AF Datasheet Revision History
Version
V0.20P
Date
2008/7/24
Page
-
Revision History
Release Version
Please note that all data and specifications are subject to change without notice. All the trade marks of products and
companies mentioned in this data sheet belong to their respective owners.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Customers using or selling these products for use
in such applications do so at their own risk and agree to fully indemnify Fintek for any damages resulting from such
improper use or sales.
F85226AF
I
July, 2008
V0.20P
Fintek
Feature Integration Technology Inc.
F85226AF
Table of Contents
General Description.............................................................................................................. 1
Features ............................................................................................................................... 1
Key Specifications ................................................................................................................ 1
Block Diagram ...................................................................................................................... 2
Pin Configuration .................................................................................................................. 3
Pin Descriptions.................................................................................................................... 3
6.1 Power Pin ....................................................................................................................... 4
6.2 Power on strapping signal .............................................................................................. 4
6.3 LPC interface .................................................................................................................. 4
6.4 ISA interface ................................................................................................................... 5
7. Function Description ........................................................................................................... 10
7.1 LPC interface: ............................................................................................................... 10
7.1.1 IO/Memory Read and Write Cycles ........................................................................... 12
7.1.2 DMA Read and Write Cycles ..................................................................................... 12
7.1.3 Booting Memory Read and Write Cycles ................................................................... 12
7.2 Serialized Interrupt........................................................................................................ 13
7.3 LPC DMA...................................................................................................................... 14
8. Registers Description ......................................................................................................... 15
8.1 Entry Key ...................................................................................................................... 15
8.2 Configuration and Control Register – Index 03h ........................................................... 15
8.3 GPIO1 Function Select Register – Index 04h ............................................................... 16
8.4 GPIO2 Function Select Register – Index 05h ............................................................... 17
8.5 System Clock Register – Index 06h.............................................................................. 17
8.6 System Power down Register – Index 10h ................................................................... 18
8.7 GPIO Port Define Register (Low byte)– Index 11h ....................................................... 18
8.8 GPIO Port Define Register (High byte)– Index 12h ...................................................... 19
8.9 Address Decoder Register (I) – Index 013h.................................................................. 19
8.10 Address Decoder Register (II) – Index 014h............................................................... 20
8.11 GPIO1x In/Out Control Register – Index 15h .............................................................. 20
8.12 GPIO Output Data Register – Index 16h..................................................................... 21
8.13 GPIO1x Input Register – Index 17h ............................................................................ 21
8.14 GPIO2x In/Out Control Register – Index 18h.............................................................. 22
8.15 GPIO2 Output Data Register – Index 19h................................................................... 22
8.16 GPIO2x Input Register – Index 1Ah............................................................................ 23
8.17 LED & IRQIN Control Register – Index 1Bh ............................................................... 23
1.
2.
3.
4.
5.
6.
F85226AF
II
July, 2008
V0.20P
Fintek
8.18
8.19
8.20
8.21
8.22
8.23
8.24
8.25
8.26
8.27
8.28
8.29
8.30
8.31
8.32
8.33
8.34
8.35
8.36
8.37
8.38
8.39
8.40
8.41
8.42
8.43
8.44
8.45
8.46
8.47
8.48
8.49
8.50
8.51
8.52
8.53
8.54
Feature Integration Technology Inc.
F85226AF
LPC Timout Setting Register – Index 1Dh .................................................................. 23
Refresh Address Register (Low Byte) – Index 1Eh..................................................... 24
Refresh Address Register (High Byte) – Index 1Fh .................................................... 24
Address1 Decode Mask Register – Index 20h............................................................ 24
Address1 Decode Register (Low Byte) – Index 21h ................................................... 24
Address1 Decode Register (High Byte) – Index 22h .................................................. 24
Address2 Decode Mask Register – Index 23h............................................................ 25
Address2 Decode Register (Low Byte) – Index 24h ................................................... 25
Address2 Decode Register (High Byte) – Index 25h .................................................. 25
ROM1 Decoder Mask Low Byte Register – Index 0x28.............................................. 25
ROM Decoder Mask (High Byte) Register – Index 0x29............................................. 26
ROM Decoder Address (Low Byte) Register – Index 0x2A......................................... 26
ROM Decoder Address (High Byte) Register – Index 0x2B ........................................ 26
ROM2 Decoder Mask Low Byte Register – Index 0x2C ............................................. 26
ROM2 Decoder Mask (High Byte) Register – Index 0x2D .......................................... 27
ROM2 Decoder Address (Low Byte) Register – Index 0x2E....................................... 27
ROM2 Decoder Address (High Byte) Register – Index 0x2F ...................................... 27
ADDR3 Decoder Mask High Byte Register – Index 0x30 ........................................... 27
ADDR3 Decoder Address Low Byte Register – Index 0x31........................................ 28
ADDR3 Decoder Address High Byte Register – Index 0x32 ....................................... 28
ADDR4 Decoder Mask High Byte Register – Index 0x33 ........................................... 28
ADDR4 Decoder Address Low Byte Register – Index 0x34........................................ 28
ADDR4 Decoder Address High Byte Register – Index 0x35 ....................................... 29
KBC Decoder Mask Register – Index 0x36 ................................................................ 29
KBC Decoder Address Low Byte Register – Index 0x37 ............................................ 29
KBC Decoder Address High Byte Register – Index 0x38............................................ 30
MC Decoder Mask Register – Index 0x39 .................................................................. 30
MC Decoder Address Low Byte Register – Index 0x3A.............................................. 30
MC Decoder Address High Byte Register – Index 0x3B ............................................. 30
RTC Decoder Mask Register – Index 0x3C ................................................................ 31
RTC Decoder Address Low Byte Register – Index 0x3D ............................................ 31
RTC Decoder Address High Byte Register – Index 0x3E ........................................... 31
IOH Decoder Mask Register – Index 0x3F ................................................................. 31
IOH Decoder Address Low Byte Register – Index 0x40 ............................................. 32
IOH Decoder Address High Byte Register – Index 0x41............................................. 32
Edge Detector Status Register – Index 0x50 .............................................................. 32
IRQ Wakeup Register (I) – Index 0x51 ....................................................................... 32
F85226AF
III
July, 2008
V0.20P
Fintek
8.55
Feature Integration Technology Inc.
F85226AF
IRQ Wakeup Register (II) – Index 0x52 ...................................................................... 33
8.56 Frame waiting control Register
Index 0x53 ............................................................ 33
8.57 VDD0 voltage value Register
Index 0x54............................................................... 34
8.58 VDD0 voltage value Register
Index 0x55............................................................... 34
8.59 CHIPID (1) Register – Index 0x5A .............................................................................. 35
8.60 CHIPID (2) Register – Index 0x5B .............................................................................. 35
8.61 VENDOR ID (1) Register – Index 0x5D ...................................................................... 35
8.62 VENDOR ID (2) Register – Index 0x5E ...................................................................... 35
8.63 SBHE control Register – Index 0xF1 .......................................................................... 35
9. Ordering Information........................................................................................................... 36
10.
Electrical characteristic .................................................................................................... 36
9.1 Absolute Maximum Ratings .......................................................................................... 36
9.2 DC Characteristics........................................................................................................ 36
11.
Package specification ...................................................................................................... 38
12.
Application Circuit ............................................................................................................ 39
F85226AF
IV
July, 2008
V0.20P
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