EN25F40
Purpose
Eon Silicon Solution Inc. (hereinafter called “Eon”) is going to provide its products’ top marking on
ICs with < cFeon > from January 1st, 2009, and without any change of the part number and the
compositions of the ICs. Eon is still keeping the promise of quality for all the products with the
same as that of Eon delivered before. Please be advised with the change and appreciate your
kindly cooperation and fully support Eon’s product family.
Eon products’ Top Marking
cFeon Top Marking Example:
cFeon
Part Number: XXXX-XXX
Lot Number: XXXXX
Date Code:
XXXXX
Continuity of Specifications
There is no change to this data sheet as a result of offering the device as an Eon product. Any
changes that have been made are the result of normal data sheet improvement and are noted in
the document revision summary, where supported. Future routine revisions will occur when
appropriate, and changes will be noted in a revision summary.
Continuity of Ordering Part Numbers
Eon continues to support existing part numbers beginning with “Eon” and “cFeon” top marking. To
order these products, during the transition please specify “Eon top marking” or “cFeon top marking”
on your purchasing orders.
For More Information
Please contact your local sales office for additional information about Eon memory solutions.
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
1
©2004 Eon Silicon Solution, Inc.,
www.eonssi.com
Rev. I, Issue Date: 2010/05/31
EN25F40
EN25F40
4 Megabit Serial Flash Memory with 4Kbytes Uniform Sector
FEATURES
•
Single power supply operation
- Full voltage range: 2.3 ~ 3.6 volt
•
Serial Interface Architecture
- SPI Compatible: Mode 0 and Mode 3
•
4 Mbit Serial Flash
- 4 M-bit/512 K-byte/2048 pages
- 256 bytes per programmable page
•
High performance
- 100MHz clock rate for 2.7~ 3.6 volt
- 75MHz clock rate for 2.3 ~ 3.6 volt
•
Low power consumption
- 12 mA typical active current
- 1
µA
typical power down current
•
-
-
-
Uniform Sector Architecture:
128 sectors of 4-Kbyte
8 blocks of 64-Kbyte
Any sector or block can be
erased individually
•
Software and Hardware Write Protection:
- Write Protect all or portion of memory via
software
- Enable/Disable protection with WP# pin
•
-
-
-
-
High performance program/erase speed
Page program time: 1.3ms typical
Sector erase time: 90ms typical
Block erase time 500ms typical
Chip erase time: 3.5 seconds typical
•
Lockable 256 byte OTP security sector
•
Minimum 100K endurance cycle
•
Package Options
-
-
-
-
-
8 pins SOP 150mil body width
8 pins SOP 200mil body width
8 contact VDFN
8 pins PDIP
All Pb-free packages are RoHS compliant
•
Commercial and industrial temperature Range
GENERAL DESCRIPTION
The EN25F40 is a 4M-bit (512K-byte) Serial Flash memory, with advanced write protection mechanisms,
accessed by a high speed SPI-compatible bus. The memory can be programmed 1 to 256 bytes at a
time, using the Page Program instruction.
The EN25F40 is designed to allow either single
Sector/Block
at a time or full chip erase operation. The
EN25F40 can be configured to protect part of the memory as the software protected mode. The device
can sustain a minimum of 100K program/erase cycles on each sector
or block.
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
2
©2004 Eon Silicon Solution, Inc.,
www.eonssi.com
Rev. I, Issue Date: 2010/05/31
EN25F40
Figure.1 CONNECTION DIAGRAMS
8 - LEAD SOP / PDIP
8 - CONTACT VDFN
Figure 2. BLOCK DIAGRAM
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
3
©2004 Eon Silicon Solution, Inc.,
www.eonssi.com
Rev. I, Issue Date: 2010/05/31
EN25F40
SIGNAL DESCRIPTION
Serial Data Input (DI)
The SPI Serial Data Input (DI) pin provides a means for instructions, addresses and data to be serially
written to (shifted into) the device. Data is latched on the rising edge of the Serial Clock (CLK) input pin.
Serial Data Output (DO)
The SPI Serial Data Output (DO) pin provides a means for data and status to be serially read from
(shifted out of) the device. Data is shifted out on the falling edge of the Serial Clock (CLK) input pin.
Serial Clock (CLK)
The SPI Serial Clock Input (CLK) pin provides the timing for serial input and output operations. ("See
SPI Mode")
Chip Select (CS#)
The SPI Chip Select (CS#) pin enables and disables device operation. When CS# is high the device is
deselected and the Serial Data Output (DO) pin is at high impedance. When deselected, the devices
power consumption will be at standby levels unless an internal erase, program or status register cycle is
in progress. When CS# is brought low the device will be selected, power consumption will increase to
active levels and instructions can be written to and data read from the device. After power-up, CS# must
transition from high to low before a new instruction will be accepted.
Hold (HOLD#)
The HOLD pin allows the device to be paused while it is actively selected. When HOLD is brought low,
while CS# is low, the DO pin will be at high impedance and signals on the DI and CLK pins will be
ignored (don’t care). The hold function can be useful when multiple devices are sharing the same SPI
signals.
Write Protect (WP#)
The Write Protect (WP#) pin can be used to prevent the Status Register from being written. Used in
conjunction with the Status Register’s Block Protect (BP0, BP1and BP2) bits and Status Register Protect
(SRP) bits, a portion or the entire memory array can be hardware protected.
Table 1. PIN Names
Symbol
CLK
DI
DO
CS#
WP#
HOLD#
Vcc
Vss
Pin Name
Serial Clock Input
Serial Data Input
Serial Data Output
Chip Enable
Write Protect
Hold Input
Supply Voltage (2.3-3.6V)
Ground
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
4
©2004 Eon Silicon Solution, Inc.,
www.eonssi.com
Rev. I, Issue Date: 2010/05/31
EN25F40
MEMORY ORGANIZATION
The memory is organized as:
524,288 bytes
Uniform Sector Architecture
8 blocks of 64-Kbyte
128 sectors of 4-Kbyte
2048 pages (256 bytes each)
Each page can be individually programmed (bits are programmed from 1 to 0). The device is Sector,
Block or Chip Erasable but not Page Erasable.
Table 2. Uniform Block Sector Architecture
Block
7
Sector
127
….
112
111
….
6
96
95
….
5
80
79
….
4
64
63
….
3
48
47
….
2
32
31
….
1
16
15
….
0
4
3
2
1
0
07F000h
….
070000h
06F000h
….
060000h
05F000h
….
050000h
04F000h
….
040000h
03F000h
….
030000h
02F000h
….
020000h
01F000h
….
010000h
00F000h
….
004000h
003000h
002000h
001000h
000000h
Address range
07FFFFh
070FFFh
06FFFFh
060FFFh
05FFFFh
050FFFh
04FFFFh
040FFFh
03FFFFh
030FFFh
02FFFFh
020FFFh
01FFFFh
010FFFh
00FFFFh
004FFFh
003FFFh
002FFFh
001FFFh
000FFFh
….
….
….
….
….
….
….
….
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
5
©2004 Eon Silicon Solution, Inc.,
www.eonssi.com
Rev. I, Issue Date: 2010/05/31
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