PRELIMINARY DATA SHEET
512M bits DDR2 SDRAM
EDE5132BABG (16M words
×
32 bits)
Specifications
•
Density: 512M bits
•
Organization
4M words
×
32 bits
×
4 banks
•
Package
128-ball FBGA
Lead-free (RoHS compliant) and Halogen-free
•
Power supply: VDD, VDDQ
=
1.5V
±
0.075V
•
Data rate: 667Mbps (max.)
•
2KB page size
Row address: A0 to A12
Column address: A0 to A8
•
Four internal banks for concurrent operation
•
Interface: SSTL_18
•
Burst lengths (BL): 4, 8
•
Burst type (BT):
Sequential (4, 8)
Interleave (4, 8)
•
/CAS Latency (CL): 3, 4, 5, 6
•
Precharge: auto precharge option for each burst
access
•
Driver strength: normal, weak, 1/4
•
Refresh: auto-refresh, self-refresh
Features
•
Double-data-rate architecture; two data transfers per
clock cycle
•
The high-speed data transfer is realized by the 4 bits
prefetch pipelined architecture
•
Bi-directional differential data strobe (DQS and /DQS)
is transmitted/received with data for capturing data at
the receiver
•
DQS is edge-aligned with data for READs; center-
aligned with data for WRITEs
•
Differential clock inputs (CK and /CK)
•
DLL aligns DQ and DQS transitions with CK
transitions
•
Commands entered on each positive CK edge; data
and data mask referenced to both edges of DQS
•
Data mask (DM) for write data
•
Posted /CAS by programmable additive latency for
better command and data bus efficiency
•
/DQS can be disabled for single-ended Data Strobe
operation
EO
•
Refresh cycles: 8192 cycles/64ms
Average refresh period
7.8µs at 0°C
≤
TC
≤ +85°C
3.9µs at
+85°C <
TC
≤ +95°C
•
Operating case temperature range
TC = 0°C to +95°C
Document No. E1372E10 (Ver. 1.0)
Date Published August 2008 (K) Japan
Printed in Japan
URL: http://www.elpida.com
L
od
Pr
This product became EOL in March, 2010.
Elpida
Memory, Inc. 2008
uc
t
EDE5132BABG
Ordering Information
Part number
EDE5132BABG-6G-F
Die
revision
A
Organization
(words
×
bits)
16M
×
32
Internal
banks
4
Speed bin
(CL-tRCD-tRP)
DDR2-667 (6-6-6)
Package
128-ball FBGA
Part Number
E D E 51 32 B A BG - 6G - F
Elpida Memory
Type
D: Monolithic Device
EO
Product Family
E: DDR2
Environment code
F: Lead Free (RoHS compliant)
and Halogen Free
Density / Bank
51: 512Mb /4-bank
Organization
32: x32
Speed
6G: DDR2-667 (6-6-6)
Package
BG: FBGA
Power Supply, Interface
B: 1.5V, SSTL_18
Die Rev.
Preliminary Data Sheet E1372E10 (Ver. 1.0)
L
od
Pr
uc
t
2
EDE5132BABG
Pin Configurations
/xxx indicates active low signal.
128-ball FBGA
1
A
VDD
DQ0 VSSQ
VSS
VSS
VSSQ DQ8
2
3
4
5
6
7
8
9
10
11
12
VDD
B
DQ1 VDDQ DQ2
VDDQ
VDDQ
DQ10 VDDQ DQ9
/DQS1
VSSQ DQ11 VSSQ
VDDQ
DQS1 VDDQ DQ12
DQ14
VSSQ DQ13 VSSQ
VDDQ
DM1 VDDQ DQ15
/RAS
/CAS ODT
VSSDL
VSS
A2
NC
C
VSSQ DQ3 VSSQ
/DQS0
D
DQ4 VDDQ DQS0
VDDQ
EO
E
F
G
H
J
K
L
M
N
P
R
S
Pin name
A0 to A12
BA0, BA1
DQ0 to DQ31
DQS0 to DQS3
/DQS0 to /DQS3
/CS
/RAS, /CAS, /WE
CKE
CK, /CK
DM0 to DM3
VSSQ DQ5 VSSQ
DQ6
DQ7 VDDQ DM0
/WE VREF CKE
NC
A3
VDD
VSS
BA0
CK
/CK
A4
VSS
BA1
A10
A9
VDD
VDDL
A1
A5
A7
A12
VSS
/CS
A6
A8
A0
A11
Note: 1. Not internally connected with die.
Preliminary Data Sheet E1372E10 (Ver. 1.0)
L
Function
Address inputs
Bank select
Data input/output
Chip select
Command input
Clock enable
Write data mask
DQ23 VDDQ DM2
VDDQ
DM3 VDDQ DQ31
DQ30
VSSQ DQ29 VSSQ
VDDQ
DQS3 VDDQ DQ28
VSSQ DQ21 VSSQ
DQ22
DQ20 VDDQ DQS2
VDDQ
VSSQ DQ19 VSSQ
/DQS2
DQ17 VDDQ DQ18
VDDQ
VDD DQ16 VSSQ
VSS
Differential data strobe
Differential clock input
od
Pr
Pin name
ODT
VDD
VSS
VDDQ
VSSQ
VREF
VDDL
VSSDL
NC*
1
/DQS3
VSSQ DQ27 VSSQ
VDDQ
DQ26 VDDQ DQ25
VSS
VSSQ DQ24 VDD
Function
ODT control
Supply voltage for internal circuit
Ground for internal circuit
Supply voltage for DQ circuit
uc
Ground for DQ circuit
Input reference voltage
Supply voltage for DLL circuit
Ground for DLL circuit
No connection
t
3
EDE5132BABG
CONTENTS
Specifications.................................................................................................................................................1
Features.........................................................................................................................................................1
Ordering Information......................................................................................................................................2
Part Number ..................................................................................................................................................2
Pin Configurations .........................................................................................................................................3
Electrical Specifications.................................................................................................................................5
Block Diagram .............................................................................................................................................24
Pin Function.................................................................................................................................................25
Command Operation ...................................................................................................................................27
Simplified State Diagram .............................................................................................................................35
Operation of DDR2 SDRAM ........................................................................................................................36
Package Drawing ........................................................................................................................................71
Recommended Soldering Conditions..........................................................................................................72
EO
Preliminary Data Sheet E1372E10 (Ver. 1.0)
L
od
Pr
uc
t
4
EDE5132BABG
Electrical Specifications
•
All voltages are referenced to VSS (GND)
•
Execute power-up and Initialization sequence before proper device operation is achieved.
Absolute Maximum Ratings
Parameter
Power supply voltage
Power supply voltage for output
Input voltage
Output voltage
Storage temperature
Power dissipation
Symbol
VDD
VDDQ
VIN
VOUT
Tstg
PD
IOUT
Rating
−1.0
to +2.3
−0.5
to +2.3
−0.5
to +2.3
−0.5
to +2.3
−55
to +100
1.0
50
Unit
V
V
V
V
°C
W
mA
Notes
1
1
1
1
1, 2
1
1
EO
Short circuit output current
Notes: 1. Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to
the device. This is a stress rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this specification is not implied. Exposure
to absolute maximum rating conditions for extended periods may affect reliability.
2. Storage temperature is the case surface temperature on the center/top side of the DRAM.
Exposing the device to stress above those listed in Absolute Maximum Ratings could cause
permanent damage. The device is not meant to be operated under conditions outside the limits
described in the operational section of this specification. Exposure to Absolute Maximum Rating
conditions for extended periods may affect device reliability.
Caution
Operating Temperature Condition
L
od
Pr
Symbol
Rating
TC
0 to +95
Parameter
Operating case temperature
Unit
°C
Notes
1, 2
Notes: 1. Operating temperature is the case surface temperature on the center/top side of the DRAM.
2. Supporting 0°C to +85°C with full AC and DC specifications.
Supporting 0°C to +85°C and being able to extend to +95°C with doubling auto-refresh commands in
frequency to a 32ms period (tREFI = 3.9µs) and higher temperature Self-Refresh entry via A7 "1" on
EMRS (2).
uc
t
Preliminary Data Sheet E1372E10 (Ver. 1.0)
5
京公网安备 11010802033920号
EEWORLD
