DATA SHEET
1G bits DDR3 SDRAM
EDJ1104BBSE (256M words
×
4 bits)
EDJ1108BBSE (128M words
×
8 bits)
EDJ1116BBSE (64M words
×
16 bits)
Specifications
•
Density: 1G bits
•
Organization
32M words
×
4 bits
×
8 banks (EDJ1104BBSE)
16M words
×
8 bits
×
8 banks (EDJ1108BBSE)
8M words
×
16 bits
×
8 banks (EDJ1116BBSE)
•
Package
78-ball FBGA (EDJ1104/1108BBSE)
96-ball FBGA (EDJ1116BBSE)
Lead-free (RoHS compliant) and Halogen-free
•
Power supply: VDD, VDDQ
=
1.5V
±
0.075V
•
Data rate
1600Mbps/1333Mbps/1066Mbps/800Mbps (max.)
•
1KB page size (EDJ1104/1108BBSE)
Row address: A0 to A13
Column address: A0 to A9, A11 (EDJ1104BBSE)
A0 to A9 (EDJ1108BBSE)
•
2KB page size (EDJ1116BBSE)
Row address: A0 to A12
Column address: A0 to A9
•
Eight internal banks for concurrent operation
•
Interface: SSTL_15
•
Burst lengths (BL): 8 and 4 with Burst Chop (BC)
•
Burst type (BT):
Sequential (8, 4 with BC)
Interleave (8, 4 with BC)
•
/CAS Latency (CL): 5, 6, 7, 8, 9, 10, 11
•
/CAS Write Latency (CWL): 5, 6, 7, 8
•
Precharge: auto precharge option for each burst
access
•
Driver strength: RZQ/7, RZQ/6 (RZQ = 240Ω)
•
Refresh: auto-refresh, self-refresh
Features
•
Double-data-rate architecture; two data transfers per
clock cycle
•
The high-speed data transfer is realized by the 8 bits
prefetch pipelined architecture
•
Bi-directional differential data strobe (DQS and /DQS)
is transmitted/received with data for capturing data at
the receiver
•
DQS is edge-aligned with data for READs; center-
aligned with data for WRITEs
•
Differential clock inputs (CK and /CK)
•
DLL aligns DQ and DQS transitions with CK
transitions
•
Commands entered on each positive CK edge; data
and data mask referenced to both edges of DQS
•
Data mask (DM) for write data
•
Posted /CAS by programmable additive latency for
better command and data bus efficiency
•
On-Die Termination (ODT) for better signal quality
Synchronous ODT
Dynamic ODT
Asynchronous ODT
•
Multi Purpose Register (MPR) for temperature read
out
•
ZQ calibration for DQ drive and ODT
•
Programmable Partial Array Self-Refresh (PASR)
•
/RESET pin for Power-up sequence and reset
function
•
SRT range:
Normal/extended
•
Programmable Output driver impedance control
EO
•
Refresh cycles
Average refresh period
7.8µs at 0°C
≤
TC
≤ +85°C
3.9µs at
+85°C <
TC
≤ +95°C
•
Operating case temperature range
TC = 0°C to +95°C
Document No. E1375E50 (Ver. 5.0)
Date Published April 2009 (K) Japan
Printed in Japan
URL: http://www.elpida.com
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This product became EOL in June, 2010.
Elpida
Memory, Inc. 2008-2009
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EDJ1104BBSE, EDJ1108BBSE, EDJ1116BBSE
Ordering Information
Part number
EDJ1104BBSE-GL-F
EDJ1104BBSE-GN-F
EDJ1104BBSE-DG-F
EDJ1104BBSE-DJ-F
EDJ1104BBSE-AE-F
EDJ1104BBSE-AG-F
EDJ1104BBSE-8A-F
EDJ1104BBSE-8C-F
EDJ1108BBSE-GL-F
EDJ1108BBSE-GN-F
EDJ1108BBSE-DG-F
EDJ1108BBSE-DJ-F
EDJ1108BBSE-AE-F
EDJ1108BBSE-AG-F
EDJ1108BBSE-8A-F
EDJ1108BBSE-8C-F
EDJ1116BBSE-GL-F
EDJ1116BBSE-GN-F
EDJ1116BBSE-DG-F
EDJ1116BBSE-DJ-F
EDJ1116BBSE-AE-F
EDJ1116BBSE-AG-F
EDJ1116BBSE-8A-F
EDJ1116BBSE-8C-F
Die
revision
Organization
(words
×
bits)
Internal
banks
JEDEC speed bin
(CL-tRCD-tRP)
DDR3-1600J (10-10-10)
DDR3-1600K (11-11-11)
DDR3-1333G (8-8-8)
DDR3-1333H (9-9-9)
DDR3-1066F (7-7-7)
DDR3-1066G (8-8-8)
DDR3-800D (5-5-5)
DDR3-800E (6-6-6)
DDR3-1600J (10-10-10)
DDR3-1600K (11-11-11)
DDR3-1333G (8-8-8)
DDR3-1333H (9-9-9)
DDR3-1066F (7-7-7)
DDR3-1066G (8-8-8)
DDR3-800D (5-5-5)
DDR3-800E (6-6-6)
DDR3-1600J (10-10-10)
DDR3-1600K (11-11-11)
DDR3-1333G (8-8-8)
DDR3-1333H (9-9-9)
DDR3-1066F (7-7-7)
DDR3-1066G (8-8-8)
DDR3-800D (5-5-5)
DDR3-800E (6-6-6)
Package
B
256M
×
4
8
78-ball FBGA
128M
×
8
EO
Part Number
Elpida Memory
Type
D: Monolithic Device
64M
×
16
96-ball FBGA
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SE: FBGA
Die Rev.
Environment code
F: Lead Free (RoHS compliant)
and Halogen Free
Product Family
J: DDR3
Density / Bank
11: 1Gb / 8-bank
Organization
04: x4
08: x8
16: x16
Speed
GL: DDR3-1600J (10-10-10)
GN: DDR3-1600K (11-11-11)
DG: DDR3-1333G (8-8-8)
DJ: DDR3-1333H (9-9-9)
AE: DDR3-1066F (7-7-7)
AG: DDR3-1066G (8-8-8)
8A: DDR3-800D (5-5-5)
8C: DDR3-800E (6-6-6)
Power Supply, Interface
B: 1.5V, SSTL_15
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Data Sheet E1375E50 (Ver. 5.0)
EDJ1104BBSE, EDJ1108BBSE, EDJ1116BBSE
Pin Configurations (×4,
×8
configuration)
/xxx indicates active low signal.
78-ball FBGA (×4 configuration)
1
A
VSS
B
VSS VSSQ
C
VDDQ
D
VSSQ
E
F
NC
/DQS
NC
VDD
NC
CK
/CK
A10(AP)
NC
VSS
NC
VSS
VDD
ZQ
VSSQ
E
VDDQ
F
NC
G
CKE
H
NC
J
VREFCA VSS
K
VDD
L
VSS
VDD
VSS
M
N
VSS /RESET A13
(Top view)
NC
A8
VSS /RESET A13
NC
A8
VSS
VSS
VDD
A5
A7
A2
A9
A1
A11
A4
A6
VSS
VDD
VDD
A3
A0
A12(/BC) BA1
VDD
VSS
BA0
BA2
NC
VREFCA VSS
NC
/CS
/WE
A10(AP)
ZQ
NC
ODT
VDD
/CAS
/CK
VDD
CKE
NC
VSS
/RAS
CK
VSS
NC
VREFDQ VDDQ
DQ2
DQS
DQ1
DQ3
VSSQ
D
VSSQ
DQ6
/DQS
DQ4
VDD
DQ7
VSS
DQ5
VSSQ
VDDQ
DQ0
DM
VSSQ VDDQ
C
VDDQ
DQ2
DQS
DQ1
DQ3
VSSQ
VDD
NC
NC
VSS
VDD
B
VSS VSSQ
DQ0
DM/TDQS
VSSQ VDDQ
78-ball FBGA (×8 configuration)
9
A
VSS
VDD
NC
NU/(/TDQS)
VSS
2
3
7
8
1
2
3
7
8
9
VDD
EO
VREFDQ VDDQ
NC
VSS
/RAS
/CAS
/WE
G
H
J
ODT
NC
VDD
/CS
VSS
BA0
A3
A5
A7
BA2
A0
A2
A9
K
L
VSS
M
N
VDD
VDD
L
A1
A11
A12(/BC) BA1
A4
A6
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Pin name
/RESET*
VDD
3
(Top view)
Pin name
A0 to A13*
3
Function
Function
Active low asynchronous reset
Supply voltage for internal
circuit
Address inputs
A10 (AP): Auto precharge
A12(/BC): Burst chop
3
BA0 to BA2*
DQ0 to DQ7
DQS, /DQS
Bank select
Data input/output
VSS
Ground for internal circuit
Supply voltage for DQ circuit
Ground for DQ circuit
Differential data strobe
VDDQ
VSSQ
TDQS, /TDQS
/CS*
3
3
Termination data strobe
Chip select
VREFDQ
VREFCA
Reference voltage for DQ
Reference voltage
Reference pin for ZQ
calibration
No connection
Not usable
/RAS, /CAS, /WE*
CKE*
3
Command input
Clock enable
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ZQ
NC*
NU*
1
2
CK, /CK
DM
ODT*
3
Differential clock input
Write data mask
ODT control
Notes: 1. Not internally connected with die.
2. Don’t connect. Internally connected.
3. Input only pins (address, command, CKE, ODT and /RESET) do not supply termination.
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Data Sheet E1375E50 (Ver. 5.0)
3
EDJ1104BBSE, EDJ1108BBSE, EDJ1116BBSE
Pin Configurations (×16 configuration)
/xxx indicates active low signal.
96-ball FBGA
1
2
3
7
8
9
A
VDDQ
DQU5 DQU7
DQU4
VDDQ
VSS
B
VSSQ
VDD
VSS
/DQSU
DQU6 VSSQ
DQSU
DQU2
VDDQ
DQU0
VSSQ
DML
VDD
C
VDDQ
DQU3
DQU1
D
E
VSSQ VDDQ
DMU
EO
Pin name
A0 to A12*
2
VSS
VSSQ
DQL0
VSSQ
VDDQ
F
VDDQ
DQL2
DQSL
DQL1
DQL3
VSSQ
VDD
VSS
VSSQ
G
VSSQ DQL6
/DQSL
H
VREFDQ VDDQ
DQL4
DQL7 DQL5 VDDQ
CK
VSS
NC
CKE
J
NC
VSS
VDD
/CS
/RAS
K
ODT
NC
/CAS
/WE
/CK
A10(AP)
VDD
ZQ
L
L
M
N
P
R
NC
VSS
BA0
A3
A5
BA2
A0
A2
NC
VREFCA
VSS
VDD
VDD
VSS
A12(/BC)
BA1
A1
A4
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VSS
VDD
A7
A9
A11
A6
VDD
VSS
T
VSS
/RESET
NC
NC
A8
(Top view)
Function
Pin name
/RESET*
VDD
Function
Active low asynchronous reset
Supply voltage for internal
circuit
Address inputs
A10(AP): Auto precharge
A12(/BC): Burst chop
Bank select
2
BA0 to BA2
DQU0 to DQU7
DQL0 to DQL7
DQSU, /DQSU
DQSL, /DQSL
/CS*
2
2
Data input/output
VSS
Ground for internal circuit
Supply voltage for DQ circuit
uc
Ground for DQ circuit
Reference voltage for DQ
Differential data strobe
Chip select
Command input
Clock enable
Differential clock input
Write data mask
ODT control
VDDQ
VSSQ
VREFDQ
VREFCA
ZQ
NC*
/RAS, /CAS, /WE*
CKE*
2
Reference voltage
CK, /CK
DMU, DML
ODT*
2
Reference pin for ZQ
calibration
No connection
t
Note: 1. Not internally connected with die.
2. Input only pins (address, command, CKE, ODT and /RESET) do not supply termination.
Data Sheet E1375E50 (Ver. 5.0)
4
EDJ1104BBSE, EDJ1108BBSE, EDJ1116BBSE
CONTENTS
Specifications.................................................................................................................................................1
Features.........................................................................................................................................................1
Ordering Information......................................................................................................................................2
Part Number ..................................................................................................................................................2
Pin Configurations (×4,
×8
configuration) ......................................................................................................3
Pin Configurations (×16 configuration) ..........................................................................................................4
Electrical Conditions ......................................................................................................................................7
Absolute Maximum Ratings .......................................................................................................................... 7
Operating Temperature Condition ................................................................................................................ 7
Recommended DC Operating Conditions (TC = 0°C to +85°C, VDD, VDDQ = 1.5V
±
0.075V) ................... 8
AC and DC Input Measurement Levels (TC = 0°C to +85°C, VDD, VDDQ = 1.5V
±
0.075V)....................... 8
VREF Tolerances ......................................................................................................................................... 9
Input Slew Rate Derating ............................................................................................................................ 10
AC and DC Logic Input Levels for Differential Signals ................................................................................ 16
AC and DC Output Measurement Levels (TC = 0°C to +85°C, VDD, VDDQ = 1.5V
±
0.075V) .................. 21
AC Overshoot/Undershoot Specification..................................................................................................... 23
Output Driver Impedance............................................................................................................................ 24
On-Die Termination (ODT) Levels and I-V Characteristics ......................................................................... 26
ODT Timing Definitions............................................................................................................................... 28
IDD Measurement Conditions (TC = 0°C to +85°C, VDD, VDDQ = 1.5V
±
0.075V) ................................... 32
EO
Data Sheet E1375E50 (Ver. 5.0)
Electrical Specifications...............................................................................................................................45
DC Characteristics 1 (TC = 0°C to +85°C, VDD, VDDQ = 1.5V
±
0.075V) ................................................. 45
DC Characteristics 2 (TC = 0°C to +85°C, VDD, VDDQ = 1.5V
±
0.075V) ................................................. 46
Pin Capacitance (TC = 25°C, VDD, VDDQ = 1.5V
±
0.075V) ..................................................................... 47
Standard Speed Bins .................................................................................................................................. 48
AC Characteristics (TC = 0°C to +85°C, VDD, VDDQ = 1.5V
±
0.075V, VSS, VSSQ = 0V)....................... 52
Block Diagram .............................................................................................................................................66
Pin Function.................................................................................................................................................67
Command Operation ...................................................................................................................................69
Command Truth Table ................................................................................................................................ 69
CKE Truth Table ......................................................................................................................................... 73
Simplified State Diagram .............................................................................................................................74
RESET and Initialization Procedure ............................................................................................................75
Power-Up and Initialization Sequence ........................................................................................................ 75
Reset and Initialization with Stable Power .................................................................................................. 76
Programming the Mode Register.................................................................................................................77
Mode Register Set Command Cycle Time (tMRD) ..................................................................................... 77
MRS Command to Non-MRS Command Delay (tMOD) ............................................................................. 77
DDR3 SDRAM Mode Register 0 [MR0] ...................................................................................................... 78
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