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EBJ21UE8BFU1-DJ-F

Description
2GB DDR3 SDRAM SO-DIMM
Categorystorage    storage   
File Size213KB,16 Pages
ManufacturerELPIDA
Websitehttp://www.elpida.com/en
Environmental Compliance
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EBJ21UE8BFU1-DJ-F Overview

2GB DDR3 SDRAM SO-DIMM

EBJ21UE8BFU1-DJ-F Parametric

Parameter NameAttribute value
Is it Rohs certified?conform to
MakerELPIDA
Parts packaging codeDMA
package instructionDIMM, DIMM204,24
Contacts204
Reach Compliance Codeunknow
ECCN codeEAR99
access modeDUAL BANK PAGE BURST
Maximum access time0.255 ns
Other featuresAUTO/SELF REFRESH
Maximum clock frequency (fCLK)667 MHz
I/O typeCOMMON
JESD-30 codeR-XDMA-N204
JESD-609 codee4
length67.6 mm
memory density34359738368 bi
Memory IC TypeDDR DRAM MODULE
memory width64
Number of functions1
Number of ports1
Number of terminals204
word count536870912 words
character code512000000
Operating modeSYNCHRONOUS
Maximum operating temperature95 °C
Minimum operating temperature
organize512MX64
Output characteristics3-STATE
Package body materialUNSPECIFIED
encapsulated codeDIMM
Encapsulate equivalent codeDIMM204,24
Package shapeRECTANGULAR
Package formMICROELECTRONIC ASSEMBLY
power supply1.5 V
Certification statusNot Qualified
refresh cycle8192
Maximum seat height3.8 mm
self refreshYES
Maximum standby current0.224 A
Maximum slew rate3 mA
Maximum supply voltage (Vsup)1.575 V
Minimum supply voltage (Vsup)1.425 V
Nominal supply voltage (Vsup)1.5 V
surface mountNO
technologyCMOS
Temperature levelOTHER
Terminal surfaceGold (Au)
Terminal formNO LEAD
Terminal pitch0.6 mm
Terminal locationDUAL
width30 mm
DATA SHEET
2GB DDR3 SDRAM SO-DIMM
EBJ21UE8BFU1 (256M words
×
64 bits, 2 Ranks)
Specifications
Density: 2GB
Organization
256M words
×
64 bits, 2 ranks
Mounting 16 pieces of 1G bits DDR3 SDRAM sealed
in FBGA
Package: 204-pin socket type small outline dual in
line memory module (SO-DIMM)
PCB height: 30.0mm
Lead pitch: 0.6mm
Lead-free (RoHS compliant) and Halogen-free
Power supply: VDD
=
1.5V
±
0.075V
Data rate: 1333Mbps (max.)
Backward compatible to1066Mbps/800Mbps/667Mbps
Eight internal banks for concurrent operation
(components)
Interface: SSTL_15
Burst lengths (BL): 8 and 4 with Burst Chop (BC)
/CAS Latency (CL): 5, 6, 7, 8, 9, 10
/CAS write latency (CWL): 5, 6, 7
Precharge: auto precharge option for each burst
access
Refresh: auto-refresh, self-refresh
Refresh cycles
Average refresh period
7.8µs at 0°C
TC
≤ +85°C
3.9µs at
+85°C <
TC
≤ +95°C
Operating case temperature range
TC = 0°C to +95°C
Features
Double-data-rate architecture: two data transfers per
clock cycle
The high-speed data transfer is realized by the 8 bits
prefetch pipelined architecture
Bi-directional differential data strobe (DQS and /DQS)
is transmitted/received with data for capturing data at
the receiver
DQS is edge-aligned with data for READs; center-
aligned with data for WRITEs
Differential clock inputs (CK and /CK)
DLL aligns DQ and DQS transitions with CK
transitions
Commands entered on each positive CK edge; data
and data mask referenced to both edges of DQS
Data mask (DM) for write data
Posted /CAS by programmable additive latency for
better command and data bus efficiency
On-Die-Termination (ODT) for better signal quality
Synchronous ODT
Dynamic ODT
Asynchronous ODT
Multi Purpose Register (MPR) for pre-defined pattern
read out
ZQ calibration for DQ drive and ODT
Programmable Partial Array Self-Refresh (PASR)
/RESET pin for Power-up sequence and reset
function
SRT range:
Normal/extended
Programmable Output driver impedance control
Document No. E1707E20 (Ver. 2.0)
Date Published December 2010 (K) Japan
Printed in Japan
URL: http://www.elpida.com
Elpida
Memory, Inc. 2010

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