CD74HC4017-Q1
HIGH-SPEED CMOS LOGIC DECADE COUNTER/DIVIDER
WITH 10 DECODED OUTPUTS
SCLS546SA − OCTOBER 2003 − REVISED APRIL 2008
D
D
D
D
D
D
D
Qualified for Automotive Applications
Fully Static Operation
Buffered Inputs
Common Reset
Positive Edge Clocking
Typical f
MAX
= 60 MHz at V
CC
= 5 V,
C
L
= 15 pF, T
A
= 25°C
Fanout (Over Temperature Range)
− Standard Outputs . . . 10 LSTTL Loads
− Bus Driver Outputs . . . 15 LSTTL Loads
Times
D
Significant Power Reduction Compared to
D
D
LSTTL Logic ICs
V
CC
Voltage = 2 V to 6 V
High Noise Immunity N
IL
or N
IH
= 30% of
V
CC
, V
CC
= 5 V
M OR PW PACKAGE
(TOP VIEW)
D
Balanced Propagation Delay and Transition
description/ordering information
8
9
The CD74HC4017 is a high-speed silicon-gate
CMOS 5-stage Johnson counter with ten decoded
outputs. Each of the decoded outputs normally is low
and sequentially goes high on the low-to-high transition clock period of the ten-clock-period cycle. The carry
(TC) output transitions low to high after output 9 goes from high to low, and can be used in conjunction with the
clock enable (CE) input to cascade several stages. CE disables counting when in the high state. A master reset
(MR) input also is provided that, when taken high, sets all the decoded outputs, except output 0, to low.
5
1
0
2
6
7
3
GND
1
2
3
4
5
6
7
16
15
14
13
12
11
10
V
CC
MR
CP
CE
TC
9
4
8
The device can drive up to ten low-power Schottky equivalent loads.
ORDERING INFORMATION
{
T
A
−40°C to 125°C
40°C
†
PACKAGE
‡
SOIC − M
Tape and reel
ORDERABLE
PART NUMBER
CD74HC4017QM96Q1
CD74HC4017QPWRQ1
TOP-SIDE
MARKING
HC4017Q
HC4017Q
TSSOP − PW Tape and reel
For the most current package and ordering information, see the Package Option Addendum at the
end of this document, or see the TI web site at http://www.ti.com.
‡
Package drawings, thermal data, and symbolization are available at http://www.ti.com/packaging.
FUNCTION TABLE
INPUTS
CP
L
X
X
↑
↓
X
H
CE
X
H
X
L
X
↑
↓
MR
L
L
H
L
L
L
L
OUTPUT STATE
†
No change
No change
0 = H, 1−9 = L
Increments counter
No change
No change
Increments counter
NOTE: H = high voltage level, L = low voltage level,
X = don’t care,
↑
= transition from low to high
level,
↓
= transition from high to low level
†
If n < 5, TC = H, otherwise TC = L
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright
2008, Texas Instruments Incorporated
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
1
CD74HC4017-Q1
HIGH-SPEED CMOS LOGIC DECADE COUNTER/DIVIDER
WITH 10 DECODED OUTPUTS
SCLS546SA − OCTOBER 2003 − REVISED APRIL 2008
logic diagram (positive logic)
3
2
4
CE
13
7
10
MR
15
1
5
6
9
11
12
0
1
2
3
4
5
6
7
8
9
TC
CP
14
Decoded
Decimal
Out
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
†
Supply voltage range, V
CC
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Input clamp current, I
IK
(V
I
< −0.5 V or V
I
> V
CC
+ 0.5 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
±20
mA
Output clamp current, I
OK
(V
O
< −0.5 V or V
O
> V
CC
+ 0.5 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
±20
mA
Source or sink current per output pin, I
O
(V
O
> −0.5 V or V
O
< V
CC
+ 0.5 V) . . . . . . . . . . . . . . . . . . . .
±25
mA
Continuous current through V
CC
or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
±50
mA
Package thermal impedance,
θ
JA
(see Note 2): M package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73°C/W
PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108°C/W
Maximum junction temperature, T
J
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C
Lead temperature (during soldering):
At distance 1/16
±
1/32 inch (1,59
±
0,79 mm) from case for 10 s max . . . . . . . . . . . . . . . . . . . . . . . 300°C
Storage temperature range, T
stg
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltages referenced to GND unless otherwise specified.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
†
2
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
CD74HC4017-Q1
HIGH-SPEED CMOS LOGIC DECADE COUNTER/DIVIDER
WITH 10 DECODED OUTPUTS
SCLS546SA − OCTOBER 2003 − REVISED APRIL 2008
recommended operating conditions (see Note 3)
MIN
V
CC
V
IH
Supply voltage
V
CC
= 2 V
High level
High-level input voltage
V
CC
= 4.5 V
V
CC
= 6 V
V
CC
= 2 V
V
IL
V
I
V
O
t
t
T
A
Low-level input voltage
Low level
Input voltage
Output voltage
V
CC
= 2 V
Input transition (rise and fall) time
Operating free-air temperature
V
CC
= 4.5 V
V
CC
= 6 V
V
CC
= 4.5 V
V
CC
= 6 V
0
0
0
0
0
−40
2
1.5
3.15
4.2
0.5
1.35
1.8
V
CC
V
CC
1000
500
400
125
°C
ns
V
V
V
V
MAX
6
UNIT
V
NOTES: 3. All unused inputs of the device must be held at V
CC
or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs,
literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
I
O
(mA)
−0.02
CMOS loads
V
OH
V
I
= V
IH
or V
IL
TTL loads
−0.02
−0.02
−4
−5.2
0.02
CMOS loads
V
OL
V
I
= V
IH
or V
IL
TTL loads
I
I
I
CC
C
IN
V
I
= V
CC
or GND
V
I
= V
CC
or GND
C
L
= 50 pF
0
0.02
0.02
4
5.2
V
CC
2V
4.5 V
6V
4.5 V
6V
2V
4.5 V
6V
4.5 V
6V
6V
6V
T
A
= 25°C
MIN
1.9
4.4
5.9
3.98
5.48
0.1
0.1
0.1
0.26
0.26
±0.1
8
10
MAX
MIN
1.9
4.4
5.9
3.7
5.2
0.1
0.1
0.1
0.4
0.4
±1
160
10
µA
µA
pF
V
V
MAX
UNIT
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DALLAS, TEXAS 75265
3
CD74HC4017-Q1
HIGH-SPEED CMOS LOGIC DECADE COUNTER/DIVIDER
WITH 10 DECODED OUTPUTS
SCLS546SA − OCTOBER 2003 − REVISED APRIL 2008
timing requirements over recommended operating free-air temperature range (unless otherwise
noted) (see Figure 1)
PARAMETER
V
CC
2V
f
max
Maximum clock frequency
4.5 V
6V
2V
CP
t
w
Pulse duration
MR
4.5 V
6V
2V
4.5 V
6V
2V
CE to CP
t
su
Setup time
MR inactive
4.5 V
6V
2V
4.5 V
6V
2V
t
h
Hold time, CE to CP
,
4.5 V
6V
T
A
= 25°C
MIN
6
30
35
80
16
14
80
16
14
75
15
13
5
5
5
0
0
0
MAX
MIN
4
20
23
120
24
20
120
24
20
110
22
19
5
5
5
0
0
0
ns
ns
ns
MHz
MAX
UNIT
4
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
CD74HC4017-Q1
HIGH-SPEED CMOS LOGIC DECADE COUNTER/DIVIDER
WITH 10 DECODED OUTPUTS
SCLS546SA − OCTOBER 2003 − REVISED APRIL 2008
switching characteristics over recommended operating free-air temperature range (unless
otherwise noted) (see Figure 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
LOAD
CAPACITANCE
V
CC
2V
Decade out
CP
TC
C
L
= 50 pF
C
L
= 15 pF
C
L
= 50 pF
C
L
= 15 pF
C
L
= 50 pF
C
L
= 15 pF
C
L
= 50 pF
C
L
= 15 pF
C
L
= 50 pF
C
L
= 15 pF
C
L
= 50 pF
C
L
= 15 pF
t
t
f
max
CP
TC, Decade out
C
L
= 50 pF
C
L
= 15 pF
4.5 V
6V
5V
2V
4.5 V
6V
5V
2V
4.5 V
6V
5V
2V
4.5 V
6V
5V
2V
4.5 V
6V
5V
2V
4.5 V
6V
5V
2V
4.5 V
6V
5V
60
19
75
15
13
110
22
19
MHz
ns
TC
19
230
46
39
345
69
59
Decade out
MR
21
230
46
39
345
69
59
TC
21
250
50
43
375
75
64
ns
Decade out
t
pd
CE
19
250
50
43
375
75
64
19
230
46
39
345
69
59
T
A
= 25°C
MIN
TYP
MAX
230
46
39
MIN
MAX
345
69
59
UNIT
operating characteristics, V
CC
= 5 V, T
A
= 25°C, input t
r
, t
f
= 6 ns, C
L
= 15 pF
PARAMETER
C
pd
Power dissipation capacitance (see Note 4)
NOTE 4: C
pd
is used to determine the dynamic power consumption per package.
P
D
= (C
pd
×
V
CC2
×
f
i
) +
Σ(C
L
×
V
CC2
×
f
O
)
f
I
= input frequency
f
O
= output frequency
C
L
= output load capacitance
V
CC
= supply voltage
TYP
39
UNIT
pF
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5
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