KIA1117AS50 datasheet, PDF - EEWORLD Datasheet

Datasheet> All Categories > Power/power management> The power supply circuit> KIA1117AS50

KIA1117AS50: DescriptionFixed Positive LDO Regulator, 5V, 1.4V Dropout, BIPolar, PDSO3, SOT-223, 4 PIN; CategoryPower/power management The power supply circuit; File Size92KB，7 Pages; ManufacturerKEC; Websitehttp://www.keccorp.com/

Download Datasheet Parametric View All

KIA1117AS50 Overview

Fixed Positive LDO Regulator, 5V, 1.4V Dropout, BIPolar, PDSO3, SOT-223, 4 PIN

KIA1117AS50 Parametric

Parameter Name	Attribute value
Maker	KEC
Parts packaging code	SOT-223
package instruction	SOT-223, 4 PIN
Contacts	4
Reach Compliance Code	unknown
ECCN code	EAR99
Maximum drop-back voltage 1	1.4 V
Maximum input voltage	10 V
Minimum input voltage	6.5 V
JESD-30 code	R-PDSO-G3
length	6.5 mm
Number of functions	1
Number of terminals	3
Working temperatureTJ-Max	125 °C
Working temperature TJ-Min	-30 °C
Maximum output voltage 1	5.15 V
Minimum output voltage 1	4.85 V
Nominal output voltage 1	5 V
Package body material	PLASTIC/EPOXY
encapsulated code	SOP
Package shape	RECTANGULAR
Package form	SMALL OUTLINE
Certification status	Not Qualified
Regulator type	FIXED POSITIVE SINGLE OUTPUT LDO REGULATOR
Maximum seat height	1.9 mm
surface mount	YES
technology	BIPOLAR
Terminal form	GULL WING
Terminal pitch	2.3 mm
Terminal location	DUAL
width	3.5 mm

Preview

Download Datasheet

View All

SEMICONDUCTOR

TECHNICAL DATA

LOW DROP FIXED AND ADJUSTABLE

POSITIVE VOLTAGE REGULATOR

The KIA1117AS/AF

is a Low Drop Voltage Regulator able

to provide up to 1A of output current, available even in adjustable

version (Vref=1.25V)

KIA1117AS/AF00~

KIA1117AS/AF50

BIPOLAR LINEAR INTEGRATED CIRCUIT

FEATURES

Low Dropout Voltage : 1.1V/Typ. (Iout=1.0A)

Very Low Quiescent Current : 2.5 /Typ.

Output Current up to 1A

Fixed Output Voltage of 1.5V, 1.8V, 2.5V, 2.85V, 3.3V, 5.0V

Adjustable Version Availability : Vref=1.25V

Internal Current and Thermal Limit

A Minimum of 10

Available in

for stability

2%(at 25 )

125

DIM

MILLIMETERS

6.5 + 0.2

3.5 + 0.2

1.8 MAX

0.7+0.15/-0.1

7 + 0.3

2.3 TYP

0.26+0.09/-0.02

3.0+0.15/-0.1

1.75 + 0.25

0.1 MAX

10 MAX

1. GND (Adj.)

2. OUTPUT

3. INPUT

Heat Sink is common to

2 (Output)

High Ripple Rejection : 80dB/Typ

Temperature Range : -30

SOT-223

LINE UP

ITEM

KIA1117AS/AF00

KIA1117AS/AF15

KIA1117AS/AF18

KIA1117AS/AF25

KIA1117AS/AF28

KIA1117AS/AF33

KIA1117AS/AF50

OUTPUT VOLTAGE (V)

Adjustable (1.25~8V)

1.5

1.8

2.5

2.85

3.3

5.0

PACKAGE

AF : DPAK

MAXIMUM RATINGS (Ta=25

CHARACTERISTIC

Input Voltage

Output Current

Power Dissipation 1

(No Heatsink)

Power Dissipation 2

(Infinite Heatsink)

Operating Temperature

Storage Temperature

S (Note)

)

SYMBOL

OUT

RATING

1.0

1.3

8.3

-30 125

-55 150

UNIT

1. GND (Adj.)

2. OUTPUT

3. INPUT

Heat Sink is common to

2 (Output)

AS : SOT-223

DIM

MILLIMETERS

6.60 + 0.2

6.10 + 0.2

5.0 + 0.2

1.10 + 0.2

2.70 + 0.2

2.30 + 0.1

1.00 MAX

2.30 + 0.2

_ 0.1

0.5 +

2.00 + 0.20

0.50 + 0.10

0.91+ 0.10

0.90 + 0.1

_ 0.10

1.00 +

0.95 MAX

DPAK

opr

stg

1.5

Note) Package Mounted on FR-4 PCB 36 18

: mounting pad for the GND Lead min. 6

2009. 10. 30

Revision No : 3

1/7

Recommended Resources

Internal functional block diagram of control chip OZ965

A circuit diagram of a household inverter power supply with excellent performance

Optocoupler TIL102/TIL103 connection equivalent circuit

Simple current sink circuit diagram

Negative voltage slope fast charger

STK0029 power amplifier circuit

Transfer Altera DE2 development board, brand new: I have an Altera DE2 development board for sale, almost new. If you need it, please contact [email]semigoodluck@126.com[/email]. I am in Beijing, and my friends in Beijing can use it as an interview b...; liukekelongman FPGA/CPLD

(Repost) Learn FPGA from scratch: [color=rgb(51, 51, 51)][backcolor=rgb(255, 255, 255)]For a long time, many newbies who have just joined the group have been repeatedly asking some very simple but confusing questions. As an administra...; 瓷娃娃 FPGA/CPLD

How to set up Max Plus to simulate without delay: How to set up Max Plus for functional simulation? After programming, the simulation waveform has a delay. How to set it so that there is no delay? I have been looking for a long time but I can't find ...; nb533 FPGA/CPLD

Low Power FPGA Design Technology: I. Introduction As system power budgets continue to shrink, new low-power components are urgently needed. For communication infrastructure, circuit board cooling, chassis miniaturization, and system r...; settleinsh FPGA/CPLD

What is the difference between an IoT gateway and an industrial router?: 1. First of all, the concepts are differentFirst of all, "gateway" is a broad concept, not a specific type of product. Any device that connects two different networks can be called a gateway. "Router"...; 蓝先生 Industrial Control Electronics

max30100 pulse heart rate: I have had this module for three weeks. Now I have finished porting the Ardunio code. However, I found that the STM32 hardware IIC writing can't even pass the first step. The simulation outputs are al...; 空心杯 Medical Electronics

Shortcut: L0 L1 L2 L3 L4 L5 L6 L7 L8 L9 LA LB LC LD LE LF LG LH LI LJ LK LL LM LN LO LP LQ LR LS LT LU LV LW LX LY LZ M0 M1 M2 M3 M4 M5 M6 M7 M8 M9 MA MB MC MD ME MF MG MH MI MJ MK ML MM MN MO MP MQ MR MS MT MU MV MW MX MY MZ N0 N1 N2 N3 N4 N5 N6 N7 N8 NA NB NC ND NE NF NG NH NI NJ NK NL NM NN NO NP NQ NR NS NT NU NV NX NZ O0 O1 O2 O3 OA OB OC OD OE OF OG OH OI OJ OK OL OM ON OP OQ OR OS OT OV OX OY OZ P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 PA PB PC PD PE PF PG PH PI PJ PK PL PM PN PO PP PQ PR PS PT PU PV PW PX PY PZ Q1 Q2 Q3 Q4 Q5 Q6 Q8 Q9 QA QB QC QE QF QG QH QK QL QM QP QR QS QT QV QW QX QY R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 RA RB RC RD RE RF RG RH RI RJ RK RL RM RN RO RP RQ RR RS RT RU RV RW RX RY RZ

Popular Components