KM29W040AT, KM29W040AIT
Document Title
512K x 8 bit NAND Flash Memory
FLASH MEMORY
Revision History
Revision No. History
0.0
1.0
1.1
Initial issue.
1) Changed Operating Voltage 2.7V ~ 5.5V
→
3.0V ~ 5.5V
Data Sheet 1999
1) Added CE don’ care mode during the data-loading and reading
t
Draft Date
April 10th 1998
July 14th 1998
April 10th 1999
Remark
Preliminary
Final
Final
The attached datasheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right
to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions about device. If you have
any questions, please contact the SAMSUNG branch office near you.
1
KM29W040AT, KM29W040AIT
512K x 8 Bit NAND Flash Memory
FEATURES
•
Voltage Supply: 3.0V~5.5V
•
Organization
- Memory Cell Array : 512K x 8
- Data Register
: 32 x 8 bit
•
Automatic Program and Erase (Typical)
- Frame Program : 32 Byte in 500µs
- Block Erase : 4K Byte in 6ms
•
32-Byte Frame Read Operation
- Random Access : 15µs(Max.)
- Serial Frame Access : 120ns(Min.)
•
Command/Address/Data Multiplexed I/O port
•
Low Operation Current (Typical)
- 10µA Standby Current
- 10mA Read/ Program/Erase Current
•
Reliable CMOS Floating-Gate Technology
- Endurance : 100K Program/Erase Cycles
•
44(40) - Lead TSOP Type II (400mil / 0.8 mm pitch)
FLASH MEMORY
GENERAL DESCRIPTION
The KM29W040A is a 512Kx8bit NAND Flash Memory. Its
NAND cell structure provides the most cost-effective solution
for Digital Audio Recording. A Program operation programs a
32-byte frame in typically 500µs and an Erase operation erase
a 4K-byte block in typically 6ms. Data in a frame can be read
out at a burst cycle rate of 120ns/byte. The I/O pins serve as
the ports for address and data input/output as well as for com-
mand inputs. The on-chip write controller automates the pro-
gram and erase operations, including program or erase pulse
repetition where required, and performs internal verification of
cell data.
The KM29W040A is an optimum solution for flash memory
application that do not require the high performance levels or
capacity of larger density flash memories. These application
include data storage in digital Telephone Answering
Devices(TAD) and other consumer applications that require
voice data storage.
PIN CONFIGURATION
PIN DESCRIPTION
Pin Name
I/O
0
~ I/O
7
CLE
Pin Function
Data Inputs/Outputs
Command Latch Enable
Address Latch Enable
Chip Enable
Read Enable
Write Enable
Write Protect
Ground Input
Ready/Busy output
Power
Ground
No Connection
VSS
CLE
ALE
WE
WP
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
I/O0
I/O1
I/O2
I/O3
VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
VCC
CE
RE
R/B
GND
N.C
N.C
N.C
N.C
N.C
ALE
CE
RE
WE
WP
GND
N.C
N.C
N.C
N.C
N.C
I/O7
I/O6
I/O5
I/O4
VCC
R/B
V
CC
V
SS
N.C
44(40) TSOP (II)
NOTE
: Connect all V
CC
and V
SS
pins of each device to common power supply outputs.
Do not leave V
CC,
V
SS
or GND inputs disconnected.
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KM29W040AT, KM29W040AIT
Figure 1. FUNCTIONAL BLOCK DIAGRAM
A
7
- A
18
X-Buffers
Latches
& Decoders
Y-Buffers
Latches
& Decoders
FLASH MEMORY
4M Bit
NAND Flash ARRAY
32Byte x 4frame x 4096row
A
0
- A
6
Page Register & S/A
Command
Command
Register
Y-Gating
I/O Buffers & Latches
CE
RE
WE
Control Logic
& High Voltage
Generator
I/O
0
Global Buffers
I/O
7
CLE ALE WP
Figure 2. ARRAY ORGANIZATION
Good Block
1Block(32Row)
(4K Byte)
The 1st Block (4KB)
1 Frame = 32 Byte
1 Row = 4 Frames = 128 Bytes
1 Block = 32 rows = 4K Bytes
1 Device = 32B x 4frames x 32rows x 128blocks
= 4Mbits
8 bit
128Byte Column
4M : 4K Row
(=128 Blocks)
1
2
3
4
Frame Register
32 Byte
I/O
0
~ I/O
7
I/O
0
1st Cycle
2nd Cycle
3rd Cycle
A
0
A
8
A
16
I/O
1
A
1
A
9
A
17
I/O
2
A
2
A
10
A
18
I/O
3
A
3
A
11
X*
(1)
I/O
4
A
4
A
12
X*
I/O
5
A
5
A
13
X*
I/O
6
A
6
A
14
*X
I/O
7
A
7
A
15
*X
Column Address (A
0
-A
4
)
Frame Address (A
5
-A
6
)
Row Address (A
7
-A
11
)
Block Address (A
12
-A
18
)
NOTE
: *(1) : X can be V
IL
or V
IH
3
KM29W040AT, KM29W040AIT
PRODUCT INTRODUCTION
FLASH MEMORY
The KM29W040A is a 4M bit memory organized as 4096 rows by 1024 columns. A 256-bit data register is connected to memory cell
arrays accommodating data transfer between the registers and the cell array during frame read and frame program operations. The
memory array is composed of unit NAND structures in which 8 cells are connected serially.
Each of the 8 cells reside in a different row. A block consists of the 32 rows, totaling 4096 unit NAND structures of 8bits each. The
array organization is shown in Figure 2. The program and read operations are executed on a frame basis, while the erase operation
is executed on a block basis. The memory array consists of 128 separately erasable 4K-byte blocks.
The KM29W040A has addresses multiplexed into 8 I/O pins. This scheme not only reduces pin count but allows systems upgrades
to higher density flash memories by maintaining consistency in system board design. Command, address and data are all written
through I/O′s by bringing WE to low while CE is low. Data is latched on the rising edge of WE. Command Latch Enable(CLE) and
Address Latch Enable(ALE) are used to multiplex command and address respectively, via the I/O pins. All commands require one
bus cycle except for Block Erase command which requires two cycles. For byte-level addressing, the 512K byte physical space
requires a 19-bit address, low row address and high row address. Frame Read and frame Program require the same three address
cycles following by a command input. In the Block Erase operation, however, only the two row address cycles are required.
Device operations are selected by writing specific commands into the command register. Table 1 defines the specific commands of
the KM29W040A.
Table 1. COMMAND SETS
Function
Read
Reset
Frame Program
Block Erase
Status read
Read ID
1st. Cycle
00h
FFh
80h
60h
70h
90h
2nd. Cycle
-
-
10h
D0h
-
-
O
O
Acceptable Command during Busy
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KM29W040AT, KM29W040AIT
PIN DESCRIPTION
Command Latch Enable(CLE)
FLASH MEMORY
The CLE input controls the path activation for commands sent to the command register. When active high, commands are latched
into the command register through the I/O ports on the rising edge of the WE signal.
Address Latch Enable(ALE)
The ALE input controls the path activation for address and input data to the internal address/data register. Addresses are latched on
the rising edge of WE with ALE high, and input data is latched when ALE is low.
Chip Enable(CE)
The CE input is the device selection control. When CE goes high during a read operation the device is returned to standby mode.
However, when the device is in the busy state during program or erase, CE high is ignored, and does not return the device to
standby mode.
Write Enable(WE)
The WE input controls writes to the I/O port. Commands, address and data are latched on the rising edge of the WE pulse.
Read Enable(RE)
The RE input is the serial data-out control, and when active drives the data onto the I/O bus. Data is valid t
REA
after the falling edge
of RE which also increments the internal column address counter by one.
I/O Port : I/O
0
~ I/O
7
The I/O pins are used to input command, address and data, and to output data during read operations. The I/O pins float to high-z
when the chip is deselected or when the outputs are disabled.
Write Protect(WP)
The WP pin provides inadvertent write/erase protection during power transitions. The internal high voltage generator is reset when
the WP pin is active low.
Ready/Busy(R/B)
The R/B output indicates the status of the device operation. When low, it indicates that a program, erase or random read operation is
in process and returns to high state upon completion. It is an open drain output and does not float to high-z condition when the chip
is deselected or when outputs are disabled.
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