89H48H12G2ZCBLGI datasheet, PDF

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89H48H12G2ZCBLGI: DescriptionFCBGA-676, Tray; CategoryThe embedded processor and controller Microcontrollers and processors; File Size521KB，45 Pages; ManufacturerIDT (Integrated Device Technology); Environmental Compliance

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89H48H12G2ZCBLGI Overview

FCBGA-676, Tray

89H48H12G2ZCBLGI Parametric

Parameter Name	Attribute value
Brand Name	Integrated Device Technology
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	IDT (Integrated Device Technology)
Parts packaging code	FCBGA
package instruction	BGA, BGA676,26X26,40
Contacts	676
Manufacturer packaging code	BLG676
Reach Compliance Code	compliant
ECCN code	EAR99
Samacsys Description	FLIP CHIP BGA 27 X 27 MM 1.0 MM PITCH
Bus compatibility	I2C; ISA; VGA; SMBUS
maximum clock frequency	125 MHz
Maximum data transfer rate	48 MBps
Drive interface standards	IEEE 1149.6AC; IEEE 1149.1
JESD-30 code	S-PBGA-B676
JESD-609 code	e1
length	27 mm
Humidity sensitivity level	4
Number of terminals	676
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Package body material	PLASTIC/EPOXY
encapsulated code	BGA
Encapsulate equivalent code	BGA676,26X26,40
Package shape	SQUARE
Package form	GRID ARRAY
Peak Reflow Temperature (Celsius)	245
power supply	1,2.5/3.3 V
Certification status	Not Qualified
Maximum seat height	3.22 mm
Maximum supply voltage	1.1 V
Minimum supply voltage	0.9 V
Nominal supply voltage	1 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal surface	Tin/Silver/Copper (Sn/Ag/Cu)
Terminal form	BALL
Terminal pitch	1 mm
Terminal location	BOTTOM
Maximum time at peak reflow temperature	NOT SPECIFIED
width	27 mm
uPs/uCs/peripheral integrated circuit type	BUS CONTROLLER, PCI

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48-Lane 12-Port PCIe® Gen2

System Interconnect Switch

89HPES48H12G2

Data Sheet

Device Overview

The 89HPES48H12G2 is a member of the IDT PRECISE™ family of

PCI Express® switching solutions. The PES48H12G2 is a 48-lane, 12-

port system interconnect switch optimized for PCI Express Gen2 packet

switching in high-performance applications, supporting multiple simulta-

neous peer-to-peer traffic flows. Target applications include servers,

storage, communications, embedded systems, and multi-host or intelli-

gent I/O based systems with inter-domain communication.



• De-emphasis

• Receive equalization

• Drive strength

Switch Partitioning

Features



High Performance Non-Blocking Switch Architecture

–

48-lane 12-port PCIe switch

• Six x8 ports switch ports each of which can bifurcate to two

x4 ports (total of twelve x4 ports)

–

Integrated SerDes supports 5.0 GT/s Gen2 and 2.5 GT/s

Gen1 operation

–

Delivers up to

48 GBps (384 Gbps)

of switching capacity

–

Supports 128 Bytes to 2 KB maximum payload size

–

Low latency cut-through architecture

–

Supports one virtual channel and eight traffic classes



Standards and Compatibility

–

PCI Express Base Specification 2.0 compliant

–

Implements the following optional PCI Express features

• Advanced Error Reporting (AER) on all ports

• End-to-End CRC (ECRC)

• Access Control Services (ACS)

• Power Budgeting Enhanced Capability

• Device Serial Number Enhanced Capability

• Sub-System ID and Sub-System Vendor ID Capability

• Internal Error Reporting ECN

• Multicast ECN

• VGA and ISA enable

• L0s and L1 ASPM

• ARI ECN



Port Configurability

–

x4 and x8 ports

• Ability to merge adjacent x4 ports to create a x8 port

–

Automatic per port link width negotiation

(x8

→

x1)

–

Crosslink support

–

Automatic lane reversal

–

Autonomous and software managed link width and speed

control

–

Per lane SerDes configuration

–

IDT proprietary feature that creates logically independent

switches in the device

–

Supports up to 12 fully independent switch partitions

–

Configurable downstream port device numbering

–

Supports dynamic reconfiguration of switch partitions

• Dynamic port reconfiguration — downstream, upstream

• Dynamic migration of ports between partitions

• Movable upstream port within and between switch partitions



Initialization / Configuration

–

Supports Root (BIOS, OS, or driver), Serial EEPROM, or

SMBus switch initialization

–

Common switch configurations are supported with pin strap-

ping (no external components)

–

Supports in-system Serial EEPROM initialization/program-

ming



Quality of Service (QoS)

–

Port arbitration

• Round robin

–

Request metering

• IDT proprietary feature that balances bandwidth among

switch ports for maximum system throughput

–

High performance switch core architecture

• Combined Input Output Queued (CIOQ) switch architecture

with large buffers



Multicast

–

Compliant to the PCI-SIG multicast ECN

–

Supports arbitrary multicasting of Posted transactions

–

Supports 64 multicast groups

–

Multicast overlay mechanism support

–

ECRC regeneration support



Clocking

–

Supports 100 MHz and 125 MHz reference clock frequencies

–

Flexible clocking modes

• Common clock

• Non-common clock

• Local port clock with SSC and port reference clock input



Hot-Plug and Hot Swap

–

Hot-plug controller on all ports

• Hot-plug supported on all downstream switch ports

IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc.

1 of 44

November 28, 2011

IDT 89HPES48H12G2 Data Sheet

SMBus Interface

The PES48H12G2 contains an SMBus master interface. This master interface allows the default configuration register values of the PES48H12G2

to be overridden following a reset with values programmed in an external serial EEPROM. The master interface is also used by an external Hot-Plug

I/O expander. Two pins make up the SMBus master interface: an SMBus clock pin and an SMBus data pin. Four pins make up the SMBus slave inter-

face: an SMBus clock pin and an SMBus data pin plus two address pins, SSMBADDR[2,1].

As shown in Figure 3, the master and slave SMBuses may only be used in a split configuration.

Switch

Processor

SMBus

Master

...

Other

SMBus

Devices

SSMBCLK

SSMBDAT

MSMBCLK

MSMBDAT

Serial

EEPROM

Hot-Plug

I/O

Expander

Figure 3 Split SMBus Interface Configuration

The switch’s SMBus master interface does not support SMBus arbitration. As a result, the switch’s SMBus master must be the only master in the

SMBus lines that connect to the serial EEPROM and I/O expander slaves. In the split configuration, the master and slave SMBuses operate as two

independent buses; thus, multi-master arbitration is not required.

Hot-Plug Interface

The PES48H12G2 supports PCI Express Hot-Plug on each downstream port. To reduce the number of pins required on the device, the

PES48H12G2 utilizes an external I/O expander, such as that used on PC motherboards, connected to the SMBus master interface. Following reset

and configuration, whenever the state of a Hot-Plug output needs to be modified, the PES48H12G2 generates an SMBus transaction to the I/O

expander with the new value of all of the outputs. Whenever a Hot-Plug input changes, the I/O expander generates an interrupt which is received on

the IOEXPINTN input pin (alternate function of GPIO) of the PES48H12G2. In response to an I/O expander interrupt, the PES48H12G2 generates an

SMBus transaction to read the state of all of the Hot-Plug inputs from the I/O expander.

General Purpose Input/Output

The PES48H12G2 provides 9 General Purpose Input/Output (GPIO) pins that may be used by the system designer as bit I/O ports. Each GPIO pin

may be configured independently as an input or output through software control. Some GPIO pins are shared with other on-chip functions. These

alternate functions may be enabled via software, SMBus slave interface, or serial configuration EEPROM.

Pin Description

The following tables list the functions of the pins provided on the PES48H12G2. Some of the functions listed may be multiplexed onto the same

pin. The active polarity of a signal is defined using a suffix. Signals ending with an “N” are defined as being active, or asserted, when at a logic zero

(low) level. All other signals (including clocks, buses, and select lines) will be interpreted as being active, or asserted, when at a logic one (high) level.

4 of 44

November 28, 2011

89H48H12G2ZCBLGI Related Products

	89H48H12G2ZCBLGI	89H48H12G2ZCBLG8	89H48H12G2ZCBLG	89H48H12G2ZCBLGI8	89H48H12G2ZCBL	89H48H12G2ZCBLI	89H48H12G2ZCBLI8
Description	FCBGA-676, Tray	FCBGA-676, Reel	FCBGA-676, Tray	FCBGA-676, Reel	FCBGA-676, Tray	FCBGA-676, Tray	FCBGA-676, Reel
Brand Name	Integrated Device Technology	Integrated Device Technology	Integrated Device Technology	Integrated Device Technology	Integrated Device Technology	Integrated Device Technology	Integrated Device Technology
Is it lead-free?	Lead free	Lead free	Lead free	Lead free	Contains lead	Contains lead	Contains lead
Is it Rohs certified?	conform to	conform to	conform to	conform to	incompatible	incompatible	incompatible
Maker	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)
Parts packaging code	FCBGA	FCBGA	FCBGA	FCBGA	FCBGA	FCBGA	FCBGA
package instruction	BGA, BGA676,26X26,40	BGA,	BGA, BGA676,26X26,40	FCBGA-676	FCBGA-676	BGA, BGA676,26X26,40	BGA,
Contacts	676	676	676	676	676	676	676
Manufacturer packaging code	BLG676	BLG676	BLG676	BLG676	BL676	BL676	BL676
Reach Compliance Code	compliant	compliant	compliant	compliant	not_compliant	not_compliant	not_compliant
ECCN code	EAR99	EAR99	EAR99	EAR99	EAR99	EAR99	EAR99
Bus compatibility	I2C; ISA; VGA; SMBUS	I2C; ISA; SMBUS; VGA	I2C; ISA; VGA; SMBUS	I2C; ISA; SMBUS; VGA	I2C; ISA; VGA; SMBUS	I2C; ISA; VGA; SMBUS	I2C; ISA; SMBUS; VGA
Maximum data transfer rate	48 MBps	48000 MBps	48 MBps	48000 MBps	48 MBps	48 MBps	48000 MBps
JESD-30 code	S-PBGA-B676	S-PBGA-B676	S-PBGA-B676	S-PBGA-B676	S-PBGA-B676	S-PBGA-B676	S-PBGA-B676
JESD-609 code	e1	e1	e1	e1	e0	e0	e0
length	27 mm	27 mm	27 mm	27 mm	27 mm	27 mm	27 mm
Humidity sensitivity level	4	4	4	4	4	4	4
Number of terminals	676	676	676	676	676	676	676
Maximum operating temperature	85 °C	70 °C	70 °C	85 °C	70 °C	85 °C	85 °C
Minimum operating temperature	-40 °C	-	-	-40 °C	-	-40 °C	-40 °C
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	BGA	BGA	BGA	BGA	BGA	BGA	BGA
Package shape	SQUARE	SQUARE	SQUARE	SQUARE	SQUARE	SQUARE	SQUARE
Package form	GRID ARRAY	GRID ARRAY	GRID ARRAY	GRID ARRAY	GRID ARRAY	GRID ARRAY	GRID ARRAY
Peak Reflow Temperature (Celsius)	245	245	245	245	225	225	225
Maximum seat height	3.22 mm	3.22 mm	3.22 mm	3.22 mm	3.22 mm	3.22 mm	3.22 mm
Maximum supply voltage	1.1 V	1.1 V	1.1 V	1.1 V	1.1 V	1.1 V	1.1 V
Minimum supply voltage	0.9 V	0.9 V	0.9 V	0.9 V	0.9 V	0.9 V	0.9 V
Nominal supply voltage	1 V	1 V	1 V	1 V	1 V	1 V	1 V
surface mount	YES	YES	YES	YES	YES	YES	YES
technology	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS
Temperature level	INDUSTRIAL	COMMERCIAL	COMMERCIAL	INDUSTRIAL	COMMERCIAL	INDUSTRIAL	INDUSTRIAL
Terminal surface	Tin/Silver/Copper (Sn/Ag/Cu)	Tin/Silver/Copper (Sn/Ag/Cu)	Tin/Silver/Copper (Sn/Ag/Cu)	Tin/Silver/Copper (Sn/Ag/Cu)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)
Terminal form	BALL	BALL	BALL	BALL	BALL	BALL	BALL
Terminal pitch	1 mm	1 mm	1 mm	1 mm	1 mm	1 mm	1 mm
Terminal location	BOTTOM	BOTTOM	BOTTOM	BOTTOM	BOTTOM	BOTTOM	BOTTOM
Maximum time at peak reflow temperature	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED
width	27 mm	27 mm	27 mm	27 mm	27 mm	27 mm	27 mm
uPs/uCs/peripheral integrated circuit type	BUS CONTROLLER, PCI	BUS CONTROLLER, PCI	BUS CONTROLLER, PCI	BUS CONTROLLER, PCI	BUS CONTROLLER, PCI	BUS CONTROLLER, PCI	BUS CONTROLLER, PCI
Samacsys Description	FLIP CHIP BGA 27 X 27 MM 1.0 MM PITCH	FLIP CHIP BGA 27 X 27 MM 1.0 MM PITCH	FLIP CHIP BGA 27 X 27 MM 1.0 MM PITCH	FLIP CHIP BGA 27 X 27 MM 1.0 MM PITCH	-	-	-
maximum clock frequency	125 MHz	-	125 MHz	-	125 MHz	125 MHz	-
Drive interface standards	IEEE 1149.6AC; IEEE 1149.1	-	IEEE 1149.6AC; IEEE 1149.1	-	IEEE 1149.6AC; IEEE 1149.1	IEEE 1149.6AC; IEEE 1149.1	-
Encapsulate equivalent code	BGA676,26X26,40	-	BGA676,26X26,40	-	BGA676,26X26,40	BGA676,26X26,40	-
power supply	1,2.5/3.3 V	-	1,2.5/3.3 V	-	1,2.5/3.3 V	1,2.5/3.3 V	-
Certification status	Not Qualified	-	Not Qualified	-	Not Qualified	Not Qualified	-

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