89H32H8G2ZCBL datasheet, PDF - EEWORLD Datasheet

Datasheet> All Categories > The embedded processor and controller> Microcontrollers and processors> 89H32H8G2ZCBL

89H32H8G2ZCBL: DescriptionFCBGA-484, Tray; CategoryThe embedded processor and controller Microcontrollers and processors; File Size471KB，41 Pages; ManufacturerIDT (Integrated Device Technology)

Download Datasheet Parametric Compare View All

89H32H8G2ZCBL Online Shopping

Suppliers	Part Number	Price	MOQ	In stock
	89H32H8G2ZCBL	-	-	View	Buy Now

89H32H8G2ZCBL Overview

FCBGA-484, Tray

89H32H8G2ZCBL Parametric

Parameter Name	Attribute value
Brand Name	Integrated Device Technology
Is it lead-free?	Contains lead
Is it Rohs certified?	incompatible
Maker	IDT (Integrated Device Technology)
Parts packaging code	FCBGA
package instruction	FCBGA-484
Contacts	484
Manufacturer packaging code	BL484
Reach Compliance Code	not_compliant
ECCN code	EAR99
Other features	OPERATES AT 125 MHZ CLOCK FREQUENCY
Bus compatibility	I2C; ISA; VGA; SMBUS
maximum clock frequency	100 MHz
Maximum data transfer rate	32 MBps
Drive interface standards	IEEE 1149.6AC; IEEE 1149.1
JESD-30 code	S-PBGA-B484
JESD-609 code	e0
length	23 mm
Humidity sensitivity level	4
Number of terminals	484
Maximum operating temperature	70 °C
Minimum operating temperature
Package body material	PLASTIC/EPOXY
encapsulated code	BGA
Encapsulate equivalent code	BGA484,22X22,40
Package shape	SQUARE
Package form	GRID ARRAY
Peak Reflow Temperature (Celsius)	225
power supply	1,2.5/3.3 V
Certification status	Not Qualified
Maximum seat height	3.32 mm
Maximum slew rate	5336 mA
Maximum supply voltage	1.1 V
Minimum supply voltage	0.9 V
Nominal supply voltage	1 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	BALL
Terminal pitch	1 mm
Terminal location	BOTTOM
Maximum time at peak reflow temperature	NOT SPECIFIED
width	23 mm
uPs/uCs/peripheral integrated circuit type	BUS CONTROLLER, PCI

Preview

Download Datasheet

View All

32-Lane 8-Port PCIe® Gen2

System Interconnect Switch

89HPES32H8G2

Data Sheet

Device Overview

The 89HPES32H8G2 is a member of the IDT PRECISE™ family of

PCI Express® switching solutions. The PES32H8G2 is a 32-lane, 8-port

system interconnect switch optimized for PCI Express Gen2 packet

switching in high-performance applications, supporting multiple simulta-

neous peer-to-peer traffic flows. Target applications include servers,

storage, communications, embedded systems, and multi-host or intelli-

gent I/O based systems with inter-domain communication.



• Receive equalization

• Drive strength

Switch Partitioning

Features



High Performance Non-Blocking Switch Architecture

–

32-lane 8-port PCIe switch

• Four x8 switch ports each of which can bifurcate to two x4

ports (total of eight x4 ports)

–

Integrated SerDes supports 5.0 GT/s Gen2 and 2.5 GT/s

Gen1 operation

–

Delivers up to 32 GBps (256 Gbps) of switching capacity

–

Supports 128 Bytes to 2 KB maximum payload size

–

Low latency cut-through architecture

–

Supports one virtual channel and eight traffic classes



Standards and Compatibility

–

PCI Express Base Specification 2.0 compliant

–

Implements the following optional PCI Express features

• Advanced Error Reporting (AER) on all ports

• End-to-End CRC (ECRC)

• Access Control Services (ACS)

• Power Budgeting Enhanced Capability

• Device Serial Number Enhanced Capability

• Sub-System ID and Sub-System Vendor ID Capability

• Internal Error Reporting ECN

• Multicast ECN

• VGA and ISA enable

• L0s and L1 ASPM

• ARI ECN



Port Configurability

–

x4 and x8 ports

• Ability to merge adjacent x4 ports to create a x8 port

–

Automatic per port link width negotiation

(x8

→

x1)

–

Crosslink support

–

Automatic lane reversal

–

Autonomous and software managed link width and speed

control

–

Per lane SerDes configuration

• De-emphasis

–

IDT proprietary feature that creates logically independent

switches in the device

–

Supports up to 8 fully independent switch partitions

–

Configurable downstream port device numbering

–

Supports dynamic reconfiguration of switch partitions

• Dynamic port reconfiguration (downstream, and upstream)

• Dynamic migration of ports between partitions

• Movable upstream port within and between switch partitions



Initialization / Configuration

–

Supports Root (BIOS, OS, or driver), Serial EEPROM, or

SMBus switch initialization

–

Common switch configurations are supported with pin strap-

ping (no external components)

–

Supports in-system Serial EEPROM initialization/program-

ming



Quality of Service (QoS)

–

Port arbitration

• Round robin

–

Request metering

• IDT proprietary feature that balances bandwidth among

switch ports for maximum system throughput

–

High performance switch core architecture

• Combined Input Output Queued (CIOQ) switch architecture

with large buffers



Multicast

–

Compliant to the PCI-SIG multicast ECN

–

Supports arbitrary multicasting of Posted transactions

–

Supports 64 multicast groups

–

Multicast overlay mechanism support

–

ECRC regeneration support



Clocking

–

Supports 100 MHz and 125 MHz reference clock frequencies

–

Flexible port clocking modes

• Common clock

• Non-common clock

• Local port clock with SSC and port reference clock input



Hot-Plug and Hot Swap

–

Hot-plug controller on all ports

• Hot-plug supported on all downstream switch ports

–

All ports support hot-plug using low-cost external I

C I/O

expanders

IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc.

1 of 40

November 28, 2011

IDT 89HPES32H8G2 Data Sheet

Each of the two SMBus interfaces contain an SMBus clock pin and an SMBus data pin. In addition, the slave SMBus has SSMBADDR1 and

SSMBADDR2 pins. As shown in Figure 3, the master and slave SMBuses may only be used in a split configuration.

Switch

Processor

SMBus

Master

...

Other

SMBus

Devices

SSMBCLK

SSMBDAT

MSMBCLK

MSMBDAT

Serial

EEPROM

Hot-Plug

I/O

Expander

Figure 3 Split SMBus Interface Configuration

The switch’s SMBus master interface does not support SMBus arbitration. As a result, the switch’s SMBus master must be the only master in the

SMBus lines that connect to the serial EEPROM and I/O expander slaves. In the split configuration, the master and slave SMBuses operate as two

independent buses; thus, multi-master arbitration is not required.

Hot-Plug Interface

The PES32H8G2 supports PCI Express Hot-Plug on each downstream port. To reduce the number of pins required on the device, the

PES32H8G2 utilizes an external I/O expander, such as that used on PC motherboards, connected to the SMBus master interface. Following reset and

configuration, whenever the state of a Hot-Plug output needs to be modified, the PES32H8G2 generates an SMBus transaction to the I/O expander

with the new value of all of the outputs. Whenever a Hot-Plug input changes, the I/O expander generates an interrupt which is received on the IOEX-

PINTN input pin (alternate function of GPIO) of the PES32H8G2. In response to an I/O expander interrupt, the PES32H8G2 generates an SMBus

transaction to read the state of all of the Hot-Plug inputs from the I/O expander.

General Purpose Input/Output

The PES32H8G2 provides 9 General Purpose Input/Output (GPIO) pins that may be used by the system designer as bit I/O ports. Each GPIO pin

may be configured independently as an input or output through software control. Some GPIO pins are shared with other on-chip functions. These

alternate functions may be enabled via software, SMBus slave interface, or serial configuration EEPROM.

4 of 40

November 28, 2011

89H32H8G2ZCBL Related Products

	89H32H8G2ZCBL	89H32H8G2ZCBLG	89H32H8G2ZCBLGI8	89H32H8G2ZCBLI8	89H32H8G2ZCBL8
Description	FCBGA-484, Tray	FCBGA-484, Tray	FCBGA-484, Reel	FCBGA-484, Reel	FCBGA-484, Reel
Brand Name	Integrated Device Technology	Integrated Device Technology	Integrated Device Technology	Integrated Device Technology	Integrated Device Technology
Is it lead-free?	Contains lead	Lead free	Lead free	Contains lead	Contains lead
Is it Rohs certified?	incompatible	conform to	conform to	incompatible	incompatible
Maker	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)
Parts packaging code	FCBGA	FCBGA	FCBGA	FCBGA	FCBGA
package instruction	FCBGA-484	BGA, BGA484,22X22,40	FCBGA-484	BGA,	BGA,
Contacts	484	484	484	484	484
Manufacturer packaging code	BL484	BLG484	BLG484	BL484	BL484
Reach Compliance Code	not_compliant	compliant	compliant	not_compliant	not_compliant
ECCN code	EAR99	EAR99	EAR99	EAR99	EAR99
Other features	OPERATES AT 125 MHZ CLOCK FREQUENCY	OPERATES AT 125 MHZ CLOCK FREQUENCY	HAVING 125MHZ INPUT REFERENCE CLOCK FREQUENCY.	HAVING 125MHZ INPUT REFERENCE CLOCK FREQUENCY.	HAVING 125MHZ INPUT REFERENCE CLOCK FREQUENCY.
Bus compatibility	I2C; ISA; VGA; SMBUS	I2C; ISA; VGA; SMBUS	I2C; ISA; SMBUS; VGA	I2C; ISA; SMBUS; VGA	I2C; ISA; SMBUS; VGA
Maximum data transfer rate	32 MBps	32 MBps	32000 MBps	32000 MBps	32000 MBps
JESD-30 code	S-PBGA-B484	S-PBGA-B484	S-PBGA-B484	S-PBGA-B484	S-PBGA-B484
JESD-609 code	e0	e1	e1	e0	e0
length	23 mm	23 mm	23 mm	23 mm	23 mm
Humidity sensitivity level	4	4	4	4	4
Number of terminals	484	484	484	484	484
Maximum operating temperature	70 °C	70 °C	85 °C	85 °C	70 °C
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	BGA	BGA	BGA	BGA	BGA
Package shape	SQUARE	SQUARE	SQUARE	SQUARE	SQUARE
Package form	GRID ARRAY	GRID ARRAY	GRID ARRAY	GRID ARRAY	GRID ARRAY
Peak Reflow Temperature (Celsius)	225	245	245	225	225
Maximum seat height	3.32 mm	3.32 mm	3.32 mm	3.32 mm	3.32 mm
Maximum supply voltage	1.1 V	1.1 V	1.1 V	1.1 V	1.1 V
Minimum supply voltage	0.9 V	0.9 V	0.9 V	0.9 V	0.9 V
Nominal supply voltage	1 V	1 V	1 V	1 V	1 V
surface mount	YES	YES	YES	YES	YES
technology	CMOS	CMOS	CMOS	CMOS	CMOS
Temperature level	COMMERCIAL	COMMERCIAL	INDUSTRIAL	INDUSTRIAL	COMMERCIAL
Terminal surface	Tin/Lead (Sn/Pb)	Tin/Silver/Copper (Sn/Ag/Cu)	Tin/Silver/Copper (Sn/Ag/Cu)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)
Terminal form	BALL	BALL	BALL	BALL	BALL
Terminal pitch	1 mm	1 mm	1 mm	1 mm	1 mm
Terminal location	BOTTOM	BOTTOM	BOTTOM	BOTTOM	BOTTOM
Maximum time at peak reflow temperature	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED
width	23 mm	23 mm	23 mm	23 mm	23 mm
uPs/uCs/peripheral integrated circuit type	BUS CONTROLLER, PCI	BUS CONTROLLER, PCI	BUS CONTROLLER, PCI	BUS CONTROLLER, PCI	BUS CONTROLLER, PCI

Recommended Resources

solid state relay circuit

Photosensitive circuit for automatic pill counting machine

Clever use of SL as gas alarm circuit diagram

Portable COMS time reminder

Incoming power outage alarm

Astable circuit with temperature compensated frequency stabilization

Shortcut: A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF AG AH AI AJ AK AL AM AN AO AP AQ AR AS AT AU AV AW AX AY AZ B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE BF BG BH BI BJ BK BL BM BN BO BP BQ BR BS BT BU BV BW BX BY BZ C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF CG CH CI CJ CK CL CM CN CO CP CQ CR CS CT CU CV CW CX CY CZ D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF DG DH DI DJ DK DL DM DN DO DP DQ DR DS DT DU DV DW DX DZ

Popular Components